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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck -check-prefix=SI %s
3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=legalizer -o - %s | FileCheck -check-prefix=CI %s
4# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck -check-prefix=VI %s
5# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s
6
7---
8name: test_fceil_s16
9body: |
10  bb.0:
11    liveins: $vgpr0
12
13    ; SI-LABEL: name: test_fceil_s16
14    ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
15    ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
16    ; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
17    ; SI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
18    ; SI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
19    ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
20    ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
21    ; CI-LABEL: name: test_fceil_s16
22    ; CI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
23    ; CI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
24    ; CI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
25    ; CI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
26    ; CI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
27    ; CI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
28    ; CI: $vgpr0 = COPY [[ANYEXT]](s32)
29    ; VI-LABEL: name: test_fceil_s16
30    ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
31    ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
32    ; VI: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
33    ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL]](s16)
34    ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
35    ; GFX9-LABEL: name: test_fceil_s16
36    ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
37    ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
38    ; GFX9: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
39    ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL]](s16)
40    ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
41    %0:_(s32) = COPY $vgpr0
42    %1:_(s16) = G_TRUNC %0
43    %2:_(s16) = G_FCEIL %1
44    %3:_(s32) = G_ANYEXT %2
45    $vgpr0 = COPY %3
46...
47
48---
49name: test_fceil_s32
50body: |
51  bb.0:
52    liveins: $vgpr0
53
54    ; SI-LABEL: name: test_fceil_s32
55    ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
56    ; SI: $vgpr0 = COPY [[COPY]](s32)
57    ; CI-LABEL: name: test_fceil_s32
58    ; CI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
59    ; CI: $vgpr0 = COPY [[COPY]](s32)
60    ; VI-LABEL: name: test_fceil_s32
61    ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
62    ; VI: $vgpr0 = COPY [[COPY]](s32)
63    ; GFX9-LABEL: name: test_fceil_s32
64    ; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
65    ; GFX9: $vgpr0 = COPY [[COPY]](s32)
66    %0:_(s32) = COPY $vgpr0
67    %1:_(s32) = G_FCEIL %0
68    $vgpr0 = COPY %0
69...
70
71---
72name: test_fceil_s64
73body: |
74  bb.0:
75    liveins: $vgpr0_vgpr1
76
77    ; SI-LABEL: name: test_fceil_s64
78    ; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
79    ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
80    ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
81    ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
82    ; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV1]](s32), [[C]](s32), [[C1]](s32)
83    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
84    ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]]
85    ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
86    ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
87    ; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495
88    ; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
89    ; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32)
90    ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32)
91    ; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
92    ; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]]
93    ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[XOR]]
94    ; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
95    ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]]
96    ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
97    ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
98    ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[COPY]], [[SELECT]]
99    ; SI: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
100    ; SI: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
101    ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s64), [[C8]]
102    ; SI: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[COPY]](s64), [[SELECT1]]
103    ; SI: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
104    ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s1), [[C9]], [[C8]]
105    ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[SELECT1]], [[SELECT2]]
106    ; SI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
107    ; SI: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
108    ; CI-LABEL: name: test_fceil_s64
109    ; CI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
110    ; CI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
111    ; CI: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
112    ; VI-LABEL: name: test_fceil_s64
113    ; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
114    ; VI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
115    ; VI: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
116    ; GFX9-LABEL: name: test_fceil_s64
117    ; GFX9: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
118    ; GFX9: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
119    ; GFX9: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
120    %0:_(s64) = COPY $vgpr0_vgpr1
121    %1:_(s64) = G_FCEIL %0
122    $vgpr0_vgpr1 = COPY %1
123...
124
125---
126name: test_fceil_v2s16
127body: |
128  bb.0:
129    liveins: $vgpr0
130
131    ; SI-LABEL: name: test_fceil_v2s16
132    ; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
133    ; SI: $vgpr0 = COPY [[COPY]](<2 x s16>)
134    ; CI-LABEL: name: test_fceil_v2s16
135    ; CI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
136    ; CI: $vgpr0 = COPY [[COPY]](<2 x s16>)
137    ; VI-LABEL: name: test_fceil_v2s16
138    ; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
139    ; VI: $vgpr0 = COPY [[COPY]](<2 x s16>)
140    ; GFX9-LABEL: name: test_fceil_v2s16
141    ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
142    ; GFX9: $vgpr0 = COPY [[COPY]](<2 x s16>)
143    %0:_(<2 x s16>) = COPY $vgpr0
144    %1:_(<2 x s16>) = G_FCEIL %0
145    $vgpr0 = COPY %0
146...
147
148---
149name: test_fceil_v2s32
150body: |
151  bb.0:
152    liveins: $vgpr0_vgpr1
153
154    ; SI-LABEL: name: test_fceil_v2s32
155    ; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
156    ; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
157    ; SI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
158    ; SI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
159    ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
160    ; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
161    ; CI-LABEL: name: test_fceil_v2s32
162    ; CI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
163    ; CI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
164    ; CI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
165    ; CI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
166    ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
167    ; CI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
168    ; VI-LABEL: name: test_fceil_v2s32
169    ; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
170    ; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
171    ; VI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
172    ; VI: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
173    ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
174    ; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
175    ; GFX9-LABEL: name: test_fceil_v2s32
176    ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
177    ; GFX9: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
178    ; GFX9: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[UV]]
179    ; GFX9: [[FCEIL1:%[0-9]+]]:_(s32) = G_FCEIL [[UV1]]
180    ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FCEIL]](s32), [[FCEIL1]](s32)
181    ; GFX9: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
182    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
183    %1:_(<2 x s32>) = G_FCEIL %0
184    $vgpr0_vgpr1 = COPY %1
185...
186
187---
188name: test_fceil_v2s64
189body: |
190  bb.0:
191    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
192
193    ; SI-LABEL: name: test_fceil_v2s64
194    ; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
195    ; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
196    ; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
197    ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
198    ; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
199    ; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV3]](s32), [[C]](s32), [[C1]](s32)
200    ; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
201    ; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]]
202    ; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
203    ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
204    ; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495
205    ; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
206    ; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32)
207    ; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32)
208    ; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
209    ; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]]
210    ; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV]], [[XOR]]
211    ; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
212    ; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]]
213    ; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
214    ; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
215    ; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV]], [[SELECT]]
216    ; SI: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
217    ; SI: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
218    ; SI: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s64), [[C8]]
219    ; SI: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV]](s64), [[SELECT1]]
220    ; SI: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
221    ; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[AND2]](s1), [[C9]], [[C8]]
222    ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[SELECT1]], [[SELECT2]]
223    ; SI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
224    ; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
225    ; SI: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV5]](s32), [[C]](s32), [[C1]](s32)
226    ; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[INT1]], [[C2]]
227    ; SI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]]
228    ; SI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND3]](s32)
229    ; SI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB1]](s32)
230    ; SI: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[ASHR1]], [[C6]]
231    ; SI: [[AND4:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[XOR1]]
232    ; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB1]](s32), [[C5]]
233    ; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB1]](s32), [[C7]]
234    ; SI: [[SELECT3:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[MV1]], [[AND4]]
235    ; SI: [[SELECT4:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV1]], [[SELECT3]]
236    ; SI: [[FCMP2:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV1]](s64), [[C8]]
237    ; SI: [[FCMP3:%[0-9]+]]:_(s1) = G_FCMP floatpred(one), [[UV1]](s64), [[SELECT4]]
238    ; SI: [[AND5:%[0-9]+]]:_(s1) = G_AND [[FCMP2]], [[FCMP3]]
239    ; SI: [[SELECT5:%[0-9]+]]:_(s64) = G_SELECT [[AND5]](s1), [[C9]], [[C8]]
240    ; SI: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[SELECT4]], [[SELECT5]]
241    ; SI: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
242    ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
243    ; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
244    ; CI-LABEL: name: test_fceil_v2s64
245    ; CI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
246    ; CI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
247    ; CI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
248    ; CI: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
249    ; CI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
250    ; CI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
251    ; VI-LABEL: name: test_fceil_v2s64
252    ; VI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
253    ; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
254    ; VI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
255    ; VI: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
256    ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
257    ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
258    ; GFX9-LABEL: name: test_fceil_v2s64
259    ; GFX9: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
260    ; GFX9: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
261    ; GFX9: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[UV]]
262    ; GFX9: [[FCEIL1:%[0-9]+]]:_(s64) = G_FCEIL [[UV1]]
263    ; GFX9: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[FCEIL]](s64), [[FCEIL1]](s64)
264    ; GFX9: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
265    %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
266    %1:_(<2 x s64>) = G_FCEIL %0
267    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
268...
269