1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s 3 4--- 5name: test_amdgcn_fdiv_fast 6body: | 7 bb.0: 8 liveins: $vgpr0, $vgpr1 9 10 ; CHECK-LABEL: name: test_amdgcn_fdiv_fast 11 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 12 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 13 ; CHECK: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY1]] 14 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1870659584 15 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 796917760 16 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216 17 ; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s32), [[C]] 18 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]] 19 ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY1]], [[SELECT]] 20 ; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FMUL]](s32) 21 ; CHECK: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[INT]] 22 ; CHECK: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[SELECT]], [[FMUL1]] 23 ; CHECK: $vgpr0 = COPY [[FMUL2]](s32) 24 %0:_(s32) = COPY $vgpr0 25 %1:_(s32) = COPY $vgpr1 26 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fdiv.fast), %0, %1 27 $vgpr0 = COPY %2 28... 29 30--- 31name: test_amdgcn_fdiv_fast_propagate_flags 32body: | 33 bb.0: 34 liveins: $vgpr0, $vgpr1 35 36 ; CHECK-LABEL: name: test_amdgcn_fdiv_fast_propagate_flags 37 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 38 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 39 ; CHECK: [[FABS:%[0-9]+]]:_(s32) = nsz G_FABS [[COPY1]] 40 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1870659584 41 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 796917760 42 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1065353216 43 ; CHECK: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(ogt), [[FABS]](s32), [[C]] 44 ; CHECK: [[SELECT:%[0-9]+]]:_(s32) = nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]] 45 ; CHECK: [[FMUL:%[0-9]+]]:_(s32) = nsz G_FMUL [[COPY1]], [[SELECT]] 46 ; CHECK: [[INT:%[0-9]+]]:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FMUL]](s32) 47 ; CHECK: [[FMUL1:%[0-9]+]]:_(s32) = nsz G_FMUL [[COPY]], [[INT]] 48 ; CHECK: [[FMUL2:%[0-9]+]]:_(s32) = nsz G_FMUL [[SELECT]], [[FMUL1]] 49 ; CHECK: $vgpr0 = COPY [[FMUL2]](s32) 50 %0:_(s32) = COPY $vgpr0 51 %1:_(s32) = COPY $vgpr1 52 %2:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fdiv.fast), %0, %1 53 $vgpr0 = COPY %2 54... 55