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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
3
4---
5name: test_sext_s32_to_s64
6body: |
7  bb.0:
8    liveins: $vgpr0
9
10    ; CHECK-LABEL: name: test_sext_s32_to_s64
11    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
12    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
13    ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
14    %0:_(s32) = COPY $vgpr0
15    %1:_(s64) = G_SEXT %0
16    $vgpr0_vgpr1 = COPY %1
17...
18
19---
20name: test_sext_s16_to_s64
21body: |
22  bb.0:
23    liveins: $vgpr0
24
25    ; CHECK-LABEL: name: test_sext_s16_to_s64
26    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
27    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32)
28    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ANYEXT]], 16
29    ; CHECK: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
30    %0:_(s32) = COPY $vgpr0
31    %1:_(s16) = G_TRUNC %0
32    %2:_(s64) = G_SEXT %1
33    $vgpr0_vgpr1 = COPY %2
34...
35
36---
37name: test_sext_s16_to_s32
38body: |
39  bb.0:
40    liveins: $vgpr0
41
42    ; CHECK-LABEL: name: test_sext_s16_to_s32
43    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
44    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
45    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
46    ; CHECK: $vgpr0 = COPY [[SEXT_INREG]](s32)
47    %0:_(s32) = COPY $vgpr0
48    %1:_(s16) = G_TRUNC %0
49    %2:_(s32) = G_SEXT %1
50    $vgpr0 = COPY %2
51...
52
53---
54name: test_sext_s24_to_s32
55body: |
56  bb.0:
57    liveins: $vgpr0
58
59    ; CHECK-LABEL: name: test_sext_s24_to_s32
60    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
61    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
62    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 24
63    ; CHECK: $vgpr0 = COPY [[SEXT_INREG]](s32)
64    %0:_(s32) = COPY $vgpr0
65    %1:_(s24) = G_TRUNC %0
66    %2:_(s32) = G_SEXT %1
67    $vgpr0 = COPY %2
68...
69
70---
71name: test_sext_i1_to_s32
72body: |
73  bb.0:
74    liveins: $vgpr0
75
76    ; CHECK-LABEL: name: test_sext_i1_to_s32
77    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
78    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
79    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 1
80    ; CHECK: $vgpr0 = COPY [[SEXT_INREG]](s32)
81    %0:_(s32) = COPY $vgpr0
82    %1:_(s1) = G_TRUNC %0
83    %2:_(s32) = G_SEXT %1
84    $vgpr0 = COPY %2
85...
86
87---
88name: test_sext_v2s16_to_v2s32
89body: |
90  bb.0:
91    liveins: $vgpr0
92
93    ; CHECK-LABEL: name: test_sext_v2s16_to_v2s32
94    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
95    ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
96    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
97    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
98    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
99    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
100    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
101    ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
102    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32)
103    ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
104    %0:_(<2 x s16>) = COPY $vgpr0
105    %1:_(<2 x s32>) = G_SEXT %0
106    $vgpr0_vgpr1 = COPY %1
107...
108
109---
110name: test_sext_v3s16_to_v3s32
111body: |
112  bb.0:
113    liveins: $vgpr0_vgpr1
114
115    ; CHECK-LABEL: name: test_sext_v3s16_to_v3s32
116    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
117    ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
118    ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
119    ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
120    ; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
121    ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
122    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
123    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
124    ; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
125    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
126    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
127    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
128    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
129    ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
130    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
131    ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
132    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32)
133    ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
134    %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
135    %1:_(<3 x s16>) = G_EXTRACT %0, 0
136    %2:_(<3 x s32>) = G_SEXT %1
137    $vgpr0_vgpr1_vgpr2 = COPY %2
138...
139
140---
141name: test_sext_v4s16_to_v4s32
142body: |
143  bb.0:
144    liveins: $vgpr0_vgpr1
145
146    ; CHECK-LABEL: name: test_sext_v4s16_to_v4s32
147    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
148    ; CHECK: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
149    ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[UV]](<2 x s16>)
150    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
151    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
152    ; CHECK: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[UV1]](<2 x s16>)
153    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32)
154    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
155    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 16
156    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
157    ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY2]], 16
158    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[BITCAST1]](s32)
159    ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY3]], 16
160    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
161    ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 16
162    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[SEXT_INREG]](s32), [[SEXT_INREG1]](s32), [[SEXT_INREG2]](s32), [[SEXT_INREG3]](s32)
163    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<4 x s32>)
164    %0:_(<4 x s16>) = COPY $vgpr0_vgpr1
165    %1:_(<4 x s32>) = G_SEXT %0
166    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
167...
168
169---
170name: test_sext_v2s32_to_v2s64
171body: |
172  bb.0:
173    liveins: $vgpr0_vgpr1
174
175    ; CHECK-LABEL: name: test_sext_v2s32_to_v2s64
176    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
177    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
178    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[UV]](s32)
179    ; CHECK: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[UV1]](s32)
180    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SEXT]](s64), [[SEXT1]](s64)
181    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
182    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
183    %1:_(<2 x s64>) = G_SEXT %0
184    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
185...
186
187---
188name: test_sext_v3s32_to_v3s64
189body: |
190  bb.0:
191    liveins: $vgpr0_vgpr1_vgpr2
192
193    ; CHECK-LABEL: name: test_sext_v3s32_to_v3s64
194    ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
195    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<3 x s32>)
196    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[UV]](s32)
197    ; CHECK: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[UV1]](s32)
198    ; CHECK: [[SEXT2:%[0-9]+]]:_(s64) = G_SEXT [[UV2]](s32)
199    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s64>) = G_BUILD_VECTOR [[SEXT]](s64), [[SEXT1]](s64), [[SEXT2]](s64)
200    ; CHECK: S_NOP 0, implicit [[BUILD_VECTOR]](<3 x s64>)
201    %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
202    %1:_(<3 x s64>) = G_SEXT %0
203    S_NOP 0, implicit %1
204
205...
206
207---
208name: test_sext_v4s32_to_v4s64
209body: |
210  bb.0:
211    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
212
213    ; CHECK-LABEL: name: test_sext_v4s32_to_v4s64
214    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
215    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<4 x s32>)
216    ; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[UV]](s32)
217    ; CHECK: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[UV1]](s32)
218    ; CHECK: [[SEXT2:%[0-9]+]]:_(s64) = G_SEXT [[UV2]](s32)
219    ; CHECK: [[SEXT3:%[0-9]+]]:_(s64) = G_SEXT [[UV3]](s32)
220    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s64>) = G_BUILD_VECTOR [[SEXT]](s64), [[SEXT1]](s64), [[SEXT2]](s64), [[SEXT3]](s64)
221    ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[BUILD_VECTOR]](<4 x s64>)
222    %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
223    %1:_(<4 x s64>) = G_SEXT %0
224    $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY %1
225...
226
227---
228name: test_sext_s8_to_s16
229body: |
230  bb.0:
231    liveins: $vgpr0
232
233    ; CHECK-LABEL: name: test_sext_s8_to_s16
234    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
235    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
236    ; CHECK: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
237    ; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C]](s16)
238    ; CHECK: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C]](s16)
239    ; CHECK: S_ENDPGM 0, implicit [[ASHR]](s16)
240    %0:_(s32) = COPY $vgpr0
241    %1:_(s8) = G_TRUNC %0
242    %2:_(s16) = G_SEXT %1
243    S_ENDPGM 0, implicit %2
244...
245
246---
247name: test_sext_s8_to_s24
248body: |
249  bb.0:
250    liveins: $vgpr0
251
252    ; CHECK-LABEL: name: test_sext_s8_to_s24
253    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
254    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
255    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
256    ; CHECK: [[TRUNC:%[0-9]+]]:_(s24) = G_TRUNC [[SEXT_INREG]](s32)
257    ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s24)
258    %0:_(s32) = COPY $vgpr0
259    %1:_(s8) = G_TRUNC %0
260    %2:_(s24) = G_SEXT %1
261    S_ENDPGM 0, implicit %2
262...
263
264---
265name: test_sext_s7_to_s32
266body: |
267  bb.0:
268    liveins: $vgpr0
269
270    ; CHECK-LABEL: name: test_sext_s7_to_s32
271    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
272    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
273    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 7
274    ; CHECK: S_ENDPGM 0, implicit [[SEXT_INREG]](s32)
275    %0:_(s32) = COPY $vgpr0
276    %1:_(s7) = G_TRUNC %0
277    %2:_(s32) = G_SEXT %1
278    S_ENDPGM 0, implicit %2
279...
280
281---
282name: test_sext_s8_to_s32
283body: |
284  bb.0:
285    liveins: $vgpr0
286
287    ; CHECK-LABEL: name: test_sext_s8_to_s32
288    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
289    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
290    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY1]], 8
291    ; CHECK: S_ENDPGM 0, implicit [[SEXT_INREG]](s32)
292    %0:_(s32) = COPY $vgpr0
293    %1:_(s8) = G_TRUNC %0
294    %2:_(s32) = G_SEXT %1
295    S_ENDPGM 0, implicit %2
296...
297
298---
299name: test_sext_s32_to_s96
300body: |
301  bb.0:
302    liveins: $vgpr0
303
304    ; CHECK-LABEL: name: test_sext_s32_to_s96
305    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
306    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
307    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
308    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ASHR]](s32)
309    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
310    ; CHECK: [[MV2:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64)
311    ; CHECK: [[TRUNC:%[0-9]+]]:_(s96) = G_TRUNC [[MV2]](s192)
312    ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s96)
313    %0:_(s32) = COPY $vgpr0
314    %1:_(s96) = G_SEXT %0
315    S_ENDPGM 0, implicit %1
316...
317
318---
319name: test_sext_s32_to_s128
320body: |
321  bb.0:
322    liveins: $vgpr0
323
324    ; CHECK-LABEL: name: test_sext_s32_to_s128
325    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
326    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
327    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
328    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ASHR]](s32)
329    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
330    ; CHECK: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64)
331    ; CHECK: S_ENDPGM 0, implicit [[MV2]](s128)
332    %0:_(s32) = COPY $vgpr0
333    %1:_(s128) = G_SEXT %0
334    S_ENDPGM 0, implicit %1
335...
336
337---
338name: test_sext_s32_to_s160
339body: |
340  bb.0:
341    liveins: $vgpr0
342
343    ; CHECK-LABEL: name: test_sext_s32_to_s160
344    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
345    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
346    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
347    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ASHR]](s32)
348    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
349    ; CHECK: [[MV2:%[0-9]+]]:_(s320) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64)
350    ; CHECK: [[TRUNC:%[0-9]+]]:_(s160) = G_TRUNC [[MV2]](s320)
351    ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s160)
352    %0:_(s32) = COPY $vgpr0
353    %1:_(s160) = G_SEXT %0
354    S_ENDPGM 0, implicit %1
355...
356
357---
358name: test_sext_s32_to_s192
359body: |
360  bb.0:
361    liveins: $vgpr0
362
363    ; CHECK-LABEL: name: test_sext_s32_to_s192
364    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
365    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
366    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
367    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ASHR]](s32)
368    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
369    ; CHECK: [[MV2:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64)
370    ; CHECK: S_ENDPGM 0, implicit [[MV2]](s192)
371    %0:_(s32) = COPY $vgpr0
372    %1:_(s192) = G_SEXT %0
373    S_ENDPGM 0, implicit %1
374...
375
376---
377name: test_sext_s32_to_s224
378body: |
379  bb.0:
380    liveins: $vgpr0
381
382    ; CHECK-LABEL: name: test_sext_s32_to_s224
383    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
384    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
385    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
386    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ASHR]](s32)
387    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
388    ; CHECK: [[MV2:%[0-9]+]]:_(s448) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64)
389    ; CHECK: [[TRUNC:%[0-9]+]]:_(s224) = G_TRUNC [[MV2]](s448)
390    ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s224)
391    %0:_(s32) = COPY $vgpr0
392    %1:_(s224) = G_SEXT %0
393    S_ENDPGM 0, implicit %1
394...
395
396---
397name: test_sext_s32_to_s256
398body: |
399  bb.0:
400    liveins: $vgpr0
401
402    ; CHECK-LABEL: name: test_sext_s32_to_s256
403    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
404    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
405    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
406    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ASHR]](s32)
407    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
408    ; CHECK: [[MV2:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64)
409    ; CHECK: S_ENDPGM 0, implicit [[MV2]](s256)
410    %0:_(s32) = COPY $vgpr0
411    %1:_(s256) = G_SEXT %0
412    S_ENDPGM 0, implicit %1
413...
414
415---
416name: test_sext_s32_to_s512
417body: |
418  bb.0:
419    liveins: $vgpr0
420
421    ; CHECK-LABEL: name: test_sext_s32_to_s512
422    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
423    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
424    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
425    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ASHR]](s32)
426    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
427    ; CHECK: [[MV2:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64)
428    ; CHECK: S_ENDPGM 0, implicit [[MV2]](s512)
429    %0:_(s32) = COPY $vgpr0
430    %1:_(s512) = G_SEXT %0
431    S_ENDPGM 0, implicit %1
432...
433
434---
435name: test_sext_s32_to_s992
436body: |
437  bb.0:
438    liveins: $vgpr0
439
440    ; CHECK-LABEL: name: test_sext_s32_to_s992
441    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
442    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
443    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
444    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ASHR]](s32)
445    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
446    ; CHECK: [[MV2:%[0-9]+]]:_(s448) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64)
447    ; CHECK: [[TRUNC:%[0-9]+]]:_(s224) = G_TRUNC [[MV2]](s448)
448    ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s224)
449    %0:_(s32) = COPY $vgpr0
450    %1:_(s224) = G_SEXT %0
451    S_ENDPGM 0, implicit %1
452...
453
454---
455
456name: test_sext_s32_to_s1024
457body: |
458  bb.0:
459    liveins: $vgpr0
460
461    ; CHECK-LABEL: name: test_sext_s32_to_s1024
462    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
463    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
464    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
465    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ASHR]](s32)
466    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
467    ; CHECK: [[MV2:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64)
468    ; CHECK: S_ENDPGM 0, implicit [[MV2]](s1024)
469    %0:_(s32) = COPY $vgpr0
470    %1:_(s1024) = G_SEXT %0
471    S_ENDPGM 0, implicit %1
472...
473
474---
475name: test_sext_s64_to_s128
476body: |
477  bb.0:
478    liveins: $vgpr0_vgpr1
479
480    ; CHECK-LABEL: name: test_sext_s64_to_s128
481    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
482    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
483    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
484    ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[ASHR]](s64)
485    ; CHECK: S_ENDPGM 0, implicit [[MV]](s128)
486    %0:_(s64) = COPY $vgpr0_vgpr1
487    %1:_(s128) = G_SEXT %0
488    S_ENDPGM 0, implicit %1
489...
490
491---
492name: test_sext_s64_to_s192
493body: |
494  bb.0:
495    liveins: $vgpr0_vgpr1
496
497    ; CHECK-LABEL: name: test_sext_s64_to_s192
498    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
499    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
500    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
501    ; CHECK: [[MV:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[COPY]](s64), [[ASHR]](s64), [[ASHR]](s64)
502    ; CHECK: S_ENDPGM 0, implicit [[MV]](s192)
503    %0:_(s64) = COPY $vgpr0_vgpr1
504    %1:_(s192) = G_SEXT %0
505    S_ENDPGM 0, implicit %1
506...
507
508---
509name: test_sext_s64_to_s256
510body: |
511  bb.0:
512    liveins: $vgpr0_vgpr1
513
514    ; CHECK-LABEL: name: test_sext_s64_to_s256
515    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
516    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
517    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
518    ; CHECK: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[COPY]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
519    ; CHECK: S_ENDPGM 0, implicit [[MV]](s256)
520    %0:_(s64) = COPY $vgpr0_vgpr1
521    %1:_(s256) = G_SEXT %0
522    S_ENDPGM 0, implicit %1
523...
524
525---
526name: test_sext_s64_to_s512
527body: |
528  bb.0:
529    liveins: $vgpr0_vgpr1
530
531    ; CHECK-LABEL: name: test_sext_s64_to_s512
532    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
533    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
534    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
535    ; CHECK: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[COPY]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
536    ; CHECK: S_ENDPGM 0, implicit [[MV]](s512)
537    %0:_(s64) = COPY $vgpr0_vgpr1
538    %1:_(s512) = G_SEXT %0
539    S_ENDPGM 0, implicit %1
540...
541
542---
543name: test_sext_s64_to_s1024
544body: |
545  bb.0:
546    liveins: $vgpr0_vgpr1
547
548    ; CHECK-LABEL: name: test_sext_s64_to_s1024
549    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
550    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
551    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
552    ; CHECK: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[COPY]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64), [[ASHR]](s64)
553    ; CHECK: S_ENDPGM 0, implicit [[MV]](s1024)
554    %0:_(s64) = COPY $vgpr0_vgpr1
555    %1:_(s1024) = G_SEXT %0
556    S_ENDPGM 0, implicit %1
557...
558
559---
560name: test_sext_s96_to_s128
561body: |
562  bb.0:
563    liveins: $vgpr0_vgpr1_vgpr2
564
565    ; CHECK-LABEL: name: test_sext_s96_to_s128
566    ; CHECK: [[COPY:%[0-9]+]]:_(s96) = COPY $vgpr0_vgpr1_vgpr2
567    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s96)
568    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
569    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV2]], [[C]](s32)
570    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
571    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[ASHR]](s32)
572    ; CHECK: [[MV2:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64)
573    ; CHECK: S_ENDPGM 0, implicit [[MV2]](s128)
574    %0:_(s96) = COPY $vgpr0_vgpr1_vgpr2
575    %1:_(s128) = G_SEXT %0
576    S_ENDPGM 0, implicit %1
577...
578
579---
580name: test_sext_s128_to_s256
581body: |
582  bb.0:
583    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
584
585    ; CHECK-LABEL: name: test_sext_s128_to_s256
586    ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
587    ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](s128)
588    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 63
589    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[UV1]], [[C]](s32)
590    ; CHECK: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV]](s64), [[UV1]](s64), [[ASHR]](s64), [[ASHR]](s64)
591    ; CHECK: S_ENDPGM 0, implicit [[MV]](s256)
592    %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
593    %1:_(s256) = G_SEXT %0
594    S_ENDPGM 0, implicit %1
595...
596
597---
598name: test_sext_s32_to_s88
599body: |
600  bb.0:
601    liveins: $vgpr0
602
603    ; CHECK-LABEL: name: test_sext_s32_to_s88
604    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
605    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
606    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
607    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
608    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C1]](s32)
609    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
610    ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C2]](s32)
611    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
612    ; CHECK: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
613    ; CHECK: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[C3]](s16)
614    ; CHECK: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[C3]](s16)
615    ; CHECK: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 7
616    ; CHECK: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[C4]](s16)
617    ; CHECK: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
618    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
619    ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[C5]]
620    ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
621    ; CHECK: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[C5]]
622    ; CHECK: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C3]](s16)
623    ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL1]]
624    ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32)
625    ; CHECK: [[AND2:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[C5]]
626    ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR2]](s32)
627    ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[C5]]
628    ; CHECK: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C3]](s16)
629    ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND2]], [[SHL2]]
630    ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
631    ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C5]]
632    ; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
633    ; CHECK: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C5]]
634    ; CHECK: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C3]](s16)
635    ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND4]], [[SHL3]]
636    ; CHECK: [[COPY3:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
637    ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C5]]
638    ; CHECK: [[COPY4:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
639    ; CHECK: [[AND7:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C5]]
640    ; CHECK: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C3]](s16)
641    ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[SHL4]]
642    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR]](s16)
643    ; CHECK: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s16)
644    ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C1]](s32)
645    ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL5]]
646    ; CHECK: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[OR2]](s16)
647    ; CHECK: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[OR3]](s16)
648    ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT3]], [[C1]](s32)
649    ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[SHL6]]
650    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR4]](s32), [[OR5]](s32)
651    ; CHECK: [[COPY5:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
652    ; CHECK: [[AND8:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C5]]
653    ; CHECK: [[COPY6:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
654    ; CHECK: [[AND9:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C5]]
655    ; CHECK: [[SHL7:%[0-9]+]]:_(s16) = G_SHL [[AND9]], [[C3]](s16)
656    ; CHECK: [[OR6:%[0-9]+]]:_(s16) = G_OR [[AND8]], [[SHL7]]
657    ; CHECK: [[COPY7:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
658    ; CHECK: [[AND10:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C5]]
659    ; CHECK: [[COPY8:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
660    ; CHECK: [[AND11:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C5]]
661    ; CHECK: [[SHL8:%[0-9]+]]:_(s16) = G_SHL [[AND11]], [[C3]](s16)
662    ; CHECK: [[OR7:%[0-9]+]]:_(s16) = G_OR [[AND10]], [[SHL8]]
663    ; CHECK: [[COPY9:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
664    ; CHECK: [[AND12:%[0-9]+]]:_(s16) = G_AND [[COPY9]], [[C5]]
665    ; CHECK: [[COPY10:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
666    ; CHECK: [[AND13:%[0-9]+]]:_(s16) = G_AND [[COPY10]], [[C5]]
667    ; CHECK: [[SHL9:%[0-9]+]]:_(s16) = G_SHL [[AND13]], [[C3]](s16)
668    ; CHECK: [[OR8:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[SHL9]]
669    ; CHECK: [[COPY11:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
670    ; CHECK: [[AND14:%[0-9]+]]:_(s16) = G_AND [[COPY11]], [[C5]]
671    ; CHECK: [[COPY12:%[0-9]+]]:_(s16) = COPY [[ASHR1]](s16)
672    ; CHECK: [[AND15:%[0-9]+]]:_(s16) = G_AND [[COPY12]], [[C5]]
673    ; CHECK: [[SHL10:%[0-9]+]]:_(s16) = G_SHL [[AND15]], [[C3]](s16)
674    ; CHECK: [[OR9:%[0-9]+]]:_(s16) = G_OR [[AND14]], [[SHL10]]
675    ; CHECK: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[OR6]](s16)
676    ; CHECK: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[OR7]](s16)
677    ; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[ZEXT5]], [[C1]](s32)
678    ; CHECK: [[OR10:%[0-9]+]]:_(s32) = G_OR [[ZEXT4]], [[SHL11]]
679    ; CHECK: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[OR8]](s16)
680    ; CHECK: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[OR9]](s16)
681    ; CHECK: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[ZEXT7]], [[C1]](s32)
682    ; CHECK: [[OR11:%[0-9]+]]:_(s32) = G_OR [[ZEXT6]], [[SHL12]]
683    ; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR10]](s32), [[OR11]](s32)
684    ; CHECK: [[MV2:%[0-9]+]]:_(s704) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]](s64)
685    ; CHECK: [[TRUNC5:%[0-9]+]]:_(s88) = G_TRUNC [[MV2]](s704)
686    ; CHECK: S_ENDPGM 0, implicit [[TRUNC5]](s88)
687    %0:_(s32) = COPY $vgpr0
688    %1:_(s88) = G_SEXT %0
689    S_ENDPGM 0, implicit %1
690...
691
692# The instruction count blows up for this and takes too long to
693# generate checks. This fails on a G_MERGE_VALUES to s4160
694#
695# ---
696# name: test_sext_s32_to_s65
697# body: |
698#   bb.0:
699#     liveins: $vgpr0
700
701#     %0:_(s32) = COPY $vgpr0
702#     %1:_(s65) = G_SEXT %0
703#     S_ENDPGM 0, implicit %1
704# ...
705
706
707# This requires fixing a bug in merge/unmerge legalization.
708# ---
709# name: test_sext_s2_to_s112
710# body: |
711#   bb.0:
712#     liveins: $vgpr0
713
714#     %0:_(s32) = COPY $vgpr0
715#     %1:_(s2) = G_TRUNC %0
716#     %2:_(s112) = G_SEXT %1
717#     S_ENDPGM 0, implicit %2
718# ...
719
720---
721name: test_sext_s112_to_s128
722body: |
723  bb.0:
724    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
725    ; CHECK-LABEL: name: test_sext_s112_to_s128
726    ; CHECK: [[COPY:%[0-9]+]]:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
727    ; CHECK: [[COPY1:%[0-9]+]]:_(s128) = COPY [[COPY]](s128)
728    ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](s128)
729    ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[UV1]], 48
730    ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[UV]](s64), [[SEXT_INREG]](s64)
731    ; CHECK: S_ENDPGM 0, implicit [[MV]](s128)
732    %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
733    %1:_(s112) = G_TRUNC %0
734    %2:_(s128) = G_SEXT %1
735    S_ENDPGM 0, implicit %2
736...
737