1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -o - %s | FileCheck %s -check-prefixes=GCN,SI 3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer -o - %s | FileCheck %s -check-prefixes=GCN,VI 4--- 5name: test_zextload_flat_i32_i8 6body: | 7 bb.0: 8 liveins: $vgpr0_vgpr1 9 10 ; SI-LABEL: name: test_zextload_flat_i32_i8 11 ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 12 ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1) 13 ; SI: $vgpr0 = COPY [[ZEXTLOAD]](s32) 14 ; VI-LABEL: name: test_zextload_flat_i32_i8 15 ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 16 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1) 17 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 18 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32) 19 ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] 20 ; VI: $vgpr0 = COPY [[AND]](s32) 21 %0:_(p0) = COPY $vgpr0_vgpr1 22 %1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 0) 23 $vgpr0 = COPY %1 24... 25--- 26name: test_zextload_flat_i32_i16 27body: | 28 bb.0: 29 liveins: $vgpr0_vgpr1 30 31 ; SI-LABEL: name: test_zextload_flat_i32_i16 32 ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 33 ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2) 34 ; SI: $vgpr0 = COPY [[ZEXTLOAD]](s32) 35 ; VI-LABEL: name: test_zextload_flat_i32_i16 36 ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 37 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2) 38 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 39 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32) 40 ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] 41 ; VI: $vgpr0 = COPY [[AND]](s32) 42 %0:_(p0) = COPY $vgpr0_vgpr1 43 %1:_(s32) = G_ZEXTLOAD %0 :: (load 2, addrspace 0) 44 $vgpr0 = COPY %1 45... 46--- 47name: test_zextload_flat_i31_i8 48body: | 49 bb.0: 50 liveins: $vgpr0_vgpr1 51 52 ; SI-LABEL: name: test_zextload_flat_i31_i8 53 ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 54 ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1) 55 ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ZEXTLOAD]](s32) 56 ; SI: $vgpr0 = COPY [[COPY1]](s32) 57 ; VI-LABEL: name: test_zextload_flat_i31_i8 58 ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 59 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1) 60 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 61 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32) 62 ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] 63 ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[AND]](s32) 64 ; VI: $vgpr0 = COPY [[COPY2]](s32) 65 %0:_(p0) = COPY $vgpr0_vgpr1 66 %1:_(s31) = G_ZEXTLOAD %0 :: (load 1, addrspace 0) 67 %2:_(s32) = G_ANYEXT %1 68 $vgpr0 = COPY %2 69... 70--- 71name: test_zextload_flat_i64_i8 72body: | 73 bb.0: 74 liveins: $vgpr0_vgpr1 75 76 ; SI-LABEL: name: test_zextload_flat_i64_i8 77 ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 78 ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1) 79 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 80 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 81 ; VI-LABEL: name: test_zextload_flat_i64_i8 82 ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 83 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1) 84 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 85 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32) 86 ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] 87 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](s32) 88 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 89 %0:_(p0) = COPY $vgpr0_vgpr1 90 %1:_(s64) = G_ZEXTLOAD %0 :: (load 1, addrspace 0) 91 $vgpr0_vgpr1 = COPY %1 92... 93--- 94name: test_zextload_flat_i64_i16 95body: | 96 bb.0: 97 liveins: $vgpr0_vgpr1 98 99 ; SI-LABEL: name: test_zextload_flat_i64_i16 100 ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 101 ; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2) 102 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32) 103 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 104 ; VI-LABEL: name: test_zextload_flat_i64_i16 105 ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 106 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2) 107 ; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 108 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32) 109 ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] 110 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[AND]](s32) 111 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 112 %0:_(p0) = COPY $vgpr0_vgpr1 113 %1:_(s64) = G_ZEXTLOAD %0 :: (load 2, addrspace 0) 114 $vgpr0_vgpr1 = COPY %1 115... 116--- 117name: test_zextload_flat_i64_i32 118body: | 119 bb.0: 120 liveins: $vgpr0_vgpr1 121 122 ; SI-LABEL: name: test_zextload_flat_i64_i32 123 ; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 124 ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4) 125 ; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32) 126 ; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 127 ; VI-LABEL: name: test_zextload_flat_i64_i32 128 ; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1 129 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4) 130 ; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32) 131 ; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) 132 %0:_(p0) = COPY $vgpr0_vgpr1 133 %1:_(s64) = G_ZEXTLOAD %0 :: (load 4, addrspace 0) 134 $vgpr0_vgpr1 = COPY %1 135... 136