1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s 3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s 4 5; TODO: Merge with DAG test 6 7define amdgpu_kernel void @is_local_vgpr(i8* addrspace(1)* %ptr.ptr) { 8; CI-LABEL: is_local_vgpr: 9; CI: ; %bb.0: 10; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 11; CI-NEXT: v_lshlrev_b32_e32 v2, 3, v0 12; CI-NEXT: s_waitcnt lgkmcnt(0) 13; CI-NEXT: v_mov_b32_e32 v0, s0 14; CI-NEXT: v_mov_b32_e32 v1, s1 15; CI-NEXT: v_add_i32_e32 v0, vcc, v0, v2 16; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 17; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] 18; CI-NEXT: s_load_dword s0, s[4:5], 0x10 19; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) 20; CI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1 21; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc 22; CI-NEXT: flat_store_dword v[0:1], v0 23; CI-NEXT: s_endpgm 24; 25; GFX9-LABEL: is_local_vgpr: 26; GFX9: ; %bb.0: 27; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 28; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0 29; GFX9-NEXT: s_waitcnt lgkmcnt(0) 30; GFX9-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1] 31; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) 32; GFX9-NEXT: s_lshl_b32 s0, s0, 16 33; GFX9-NEXT: s_waitcnt vmcnt(0) 34; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1 35; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc 36; GFX9-NEXT: global_store_dword v[0:1], v0, off 37; GFX9-NEXT: s_endpgm 38 %id = call i32 @llvm.amdgcn.workitem.id.x() 39 %gep = getelementptr inbounds i8*, i8* addrspace(1)* %ptr.ptr, i32 %id 40 %ptr = load volatile i8*, i8* addrspace(1)* %gep 41 %val = call i1 @llvm.amdgcn.is.shared(i8* %ptr) 42 %ext = zext i1 %val to i32 43 store i32 %ext, i32 addrspace(1)* undef 44 ret void 45} 46 47define amdgpu_kernel void @is_local_sgpr(i8* %ptr) { 48; CI-LABEL: is_local_sgpr: 49; CI: ; %bb.0: 50; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 51; CI-NEXT: s_waitcnt lgkmcnt(0) 52; CI-NEXT: s_load_dword s0, s[4:5], 0x10 53; CI-NEXT: s_waitcnt lgkmcnt(0) 54; CI-NEXT: s_cmp_lg_u32 s1, s0 55; CI-NEXT: s_cselect_b32 s0, 1, 0 56; CI-NEXT: s_and_b32 s0, s0, 1 57; CI-NEXT: s_cmp_lg_u32 s0, 0 58; CI-NEXT: s_cbranch_scc1 BB1_2 59; CI-NEXT: ; %bb.1: ; %bb0 60; CI-NEXT: v_mov_b32_e32 v0, 0 61; CI-NEXT: flat_store_dword v[0:1], v0 62; CI-NEXT: BB1_2: ; %bb1 63; CI-NEXT: s_endpgm 64; 65; GFX9-LABEL: is_local_sgpr: 66; GFX9: ; %bb.0: 67; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 68; GFX9-NEXT: s_waitcnt lgkmcnt(0) 69; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) 70; GFX9-NEXT: s_lshl_b32 s0, s0, 16 71; GFX9-NEXT: s_cmp_lg_u32 s1, s0 72; GFX9-NEXT: s_cselect_b32 s0, 1, 0 73; GFX9-NEXT: s_and_b32 s0, s0, 1 74; GFX9-NEXT: s_cmp_lg_u32 s0, 0 75; GFX9-NEXT: s_cbranch_scc1 BB1_2 76; GFX9-NEXT: ; %bb.1: ; %bb0 77; GFX9-NEXT: v_mov_b32_e32 v0, 0 78; GFX9-NEXT: global_store_dword v[0:1], v0, off 79; GFX9-NEXT: BB1_2: ; %bb1 80; GFX9-NEXT: s_endpgm 81 %val = call i1 @llvm.amdgcn.is.shared(i8* %ptr) 82 br i1 %val, label %bb0, label %bb1 83 84bb0: 85 store volatile i32 0, i32 addrspace(1)* undef 86 br label %bb1 87 88bb1: 89 ret void 90} 91 92declare i32 @llvm.amdgcn.workitem.id.x() #0 93declare i1 @llvm.amdgcn.is.shared(i8* nocapture) #0 94 95attributes #0 = { nounwind readnone speculatable } 96