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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
4
5---
6name: ds_ordered_add_ss
7legalized: true
8
9body: |
10  bb.0:
11    liveins: $sgpr0, $sgpr1
12    ; CHECK-LABEL: name: ds_ordered_add_ss
13    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
14    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
15    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
16    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.ordered.add), [[COPY]](s32), [[COPY2]](s32), 0, 0, 0, 0, 0, 0
17    %0:_(s32) = COPY $sgpr0
18    %1:_(s32) = COPY $sgpr1
19    %2:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.ordered.add), %0, %1, 0, 0, 0, 0, 0, 0
20...
21
22---
23name: ds_ordered_add_vs
24legalized: true
25
26body: |
27  bb.0:
28    liveins: $vgpr0, $sgpr0
29    ; CHECK-LABEL: name: ds_ordered_add_vs
30    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
31    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
32    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
33    ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY]](s32), implicit $exec
34    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.ordered.add), [[V_READFIRSTLANE_B32_]](s32), [[COPY2]](s32), 0, 0, 0, 0, 0, 0
35    %0:_(s32) = COPY $vgpr0
36    %1:_(s32) = COPY $sgpr0
37    %2:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.ordered.add), %0, %1, 0, 0, 0, 0, 0, 0
38...
39
40---
41name: ds_ordered_add_vv
42legalized: true
43
44body: |
45  bb.0:
46    liveins: $vgpr0, $vgpr1
47    ; CHECK-LABEL: name: ds_ordered_add_vv
48    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
49    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
50    ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY]](s32), implicit $exec
51    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.ordered.add), [[V_READFIRSTLANE_B32_]](s32), [[COPY1]](s32), 0, 0, 0, 0, 0, 0
52    %0:_(s32) = COPY $vgpr0
53    %1:_(s32) = COPY $vgpr1
54    %2:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.ordered.add), %0, %1, 0, 0, 0, 0, 0, 0
55...
56
57---
58name: ds_ordered_add_sv
59legalized: true
60
61body: |
62  bb.0:
63    liveins: $vgpr0, $sgpr0
64    ; CHECK-LABEL: name: ds_ordered_add_sv
65    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
66    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
67    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.ordered.add), [[COPY]](s32), [[COPY1]](s32), 0, 0, 0, 0, 0, 0
68    %0:_(s32) = COPY $sgpr0
69    %1:_(s32) = COPY $vgpr0
70    %2:_(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.ordered.add), %0, %1, 0, 0, 0, 0, 0, 0
71...
72