1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s 3# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s 4 5--- 6name: interp_p1_f16_ss 7legalized: true 8tracksRegLiveness: true 9 10body: | 11 bb.0: 12 liveins: $sgpr0, $sgpr1 13 14 ; CHECK-LABEL: name: interp_p1_f16_ss 15 ; CHECK: liveins: $sgpr0, $sgpr1 16 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 17 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 18 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) 19 ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1.f16), [[COPY2]](s32), 1, 1, 1, [[COPY1]](s32) 20 %0:_(s32) = COPY $sgpr0 21 %1:_(s32) = COPY $sgpr1 22 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1.f16), %0, 1, 1, 1, %1 23... 24 25--- 26name: interp_p1_f16_sv 27legalized: true 28tracksRegLiveness: true 29 30body: | 31 bb.0: 32 liveins: $sgpr0, $vgpr0 33 ; CHECK-LABEL: name: interp_p1_f16_sv 34 ; CHECK: liveins: $sgpr0, $vgpr0 35 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 36 ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0 37 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) 38 ; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32(s32) = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec 39 ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1.f16), [[COPY2]](s32), 1, 1, 1, [[V_READFIRSTLANE_B32_]](s32) 40 %0:_(s32) = COPY $sgpr0 41 %1:_(s32) = COPY $vgpr0 42 %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.interp.p1.f16), %0, 1, 1, 1, %1 43... 44