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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name: update_dpp_ss
6legalized: true
7tracksRegLiveness: true
8body: |
9  bb.0:
10    liveins: $sgpr0, $sgpr1
11
12    ; CHECK-LABEL: name: update_dpp_ss
13    ; CHECK: liveins: $sgpr0, $sgpr1
14    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
15    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
16    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
17    ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
18    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.update.dpp), [[COPY2]](p3), [[COPY3]](s32), 0, 0, 0, 0
19    %0:_(p3) = COPY $sgpr0
20    %1:_(s32) = COPY $sgpr1
21    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.update.dpp), %0, %1, 0, 0, 0, 0
22
23...
24
25---
26name: update_dpp_sv
27legalized: true
28tracksRegLiveness: true
29body: |
30  bb.0:
31    liveins: $sgpr0, $vgpr0
32
33    ; CHECK-LABEL: name: update_dpp_sv
34    ; CHECK: liveins: $sgpr0, $vgpr0
35    ; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
36    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
37    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
38    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.update.dpp), [[COPY2]](p3), [[COPY1]](s32), 0, 0, 0, 0
39    %0:_(p3) = COPY $sgpr0
40    %1:_(s32) = COPY $vgpr0
41    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.update.dpp), %0, %1, 0, 0, 0, 0
42
43...
44
45---
46name: update_dpp_vs
47legalized: true
48tracksRegLiveness: true
49body: |
50  bb.0:
51    liveins: $vgpr0, $sgpr0
52
53    ; CHECK-LABEL: name: update_dpp_vs
54    ; CHECK: liveins: $vgpr0, $sgpr0
55    ; CHECK: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
56    ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
57    ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
58    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.update.dpp), [[COPY]](p3), [[COPY2]](s32), 0, 0, 0, 0
59    %0:_(p3) = COPY $vgpr0
60    %1:_(s32) = COPY $sgpr0
61    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.update.dpp), %0, %1, 0, 0, 0, 0
62
63...
64
65---
66name: update_dpp_vv
67legalized: true
68tracksRegLiveness: true
69body: |
70  bb.0:
71    liveins: $vgpr0, $vgpr1
72
73    ; CHECK-LABEL: name: update_dpp_vv
74    ; CHECK: liveins: $vgpr0, $vgpr1
75    ; CHECK: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
76    ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
77    ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.update.dpp), [[COPY]](p3), [[COPY1]](s32), 0, 0, 0, 0
78    %0:_(p3) = COPY $vgpr0
79    %1:_(s32) = COPY $vgpr1
80    %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.update.dpp), %0, %1, 0, 0, 0, 0
81
82...
83