1; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-annotate-kernel-features %s | FileCheck -check-prefix=HSA %s 2 3declare i32 @llvm.amdgcn.workgroup.id.x() #0 4declare i32 @llvm.amdgcn.workgroup.id.y() #0 5declare i32 @llvm.amdgcn.workgroup.id.z() #0 6 7declare i32 @llvm.amdgcn.workitem.id.x() #0 8declare i32 @llvm.amdgcn.workitem.id.y() #0 9declare i32 @llvm.amdgcn.workitem.id.z() #0 10 11declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0 12declare i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0 13declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0 14declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0 15declare i64 @llvm.amdgcn.dispatch.id() #0 16 17; HSA: define void @use_workitem_id_x() #1 { 18define void @use_workitem_id_x() #1 { 19 %val = call i32 @llvm.amdgcn.workitem.id.x() 20 store volatile i32 %val, i32 addrspace(1)* undef 21 ret void 22} 23 24; HSA: define void @use_workitem_id_y() #2 { 25define void @use_workitem_id_y() #1 { 26 %val = call i32 @llvm.amdgcn.workitem.id.y() 27 store volatile i32 %val, i32 addrspace(1)* undef 28 ret void 29} 30 31; HSA: define void @use_workitem_id_z() #3 { 32define void @use_workitem_id_z() #1 { 33 %val = call i32 @llvm.amdgcn.workitem.id.z() 34 store volatile i32 %val, i32 addrspace(1)* undef 35 ret void 36} 37 38; HSA: define void @use_workgroup_id_x() #4 { 39define void @use_workgroup_id_x() #1 { 40 %val = call i32 @llvm.amdgcn.workgroup.id.x() 41 store volatile i32 %val, i32 addrspace(1)* undef 42 ret void 43} 44 45; HSA: define void @use_workgroup_id_y() #5 { 46define void @use_workgroup_id_y() #1 { 47 %val = call i32 @llvm.amdgcn.workgroup.id.y() 48 store volatile i32 %val, i32 addrspace(1)* undef 49 ret void 50} 51 52; HSA: define void @use_workgroup_id_z() #6 { 53define void @use_workgroup_id_z() #1 { 54 %val = call i32 @llvm.amdgcn.workgroup.id.z() 55 store volatile i32 %val, i32 addrspace(1)* undef 56 ret void 57} 58 59; HSA: define void @use_dispatch_ptr() #7 { 60define void @use_dispatch_ptr() #1 { 61 %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 62 store volatile i8 addrspace(4)* %dispatch.ptr, i8 addrspace(4)* addrspace(1)* undef 63 ret void 64} 65 66; HSA: define void @use_queue_ptr() #8 { 67define void @use_queue_ptr() #1 { 68 %queue.ptr = call i8 addrspace(4)* @llvm.amdgcn.queue.ptr() 69 store volatile i8 addrspace(4)* %queue.ptr, i8 addrspace(4)* addrspace(1)* undef 70 ret void 71} 72 73; HSA: define void @use_dispatch_id() #9 { 74define void @use_dispatch_id() #1 { 75 %val = call i64 @llvm.amdgcn.dispatch.id() 76 store volatile i64 %val, i64 addrspace(1)* undef 77 ret void 78} 79 80; HSA: define void @use_workgroup_id_y_workgroup_id_z() #10 { 81define void @use_workgroup_id_y_workgroup_id_z() #1 { 82 %val0 = call i32 @llvm.amdgcn.workgroup.id.y() 83 %val1 = call i32 @llvm.amdgcn.workgroup.id.z() 84 store volatile i32 %val0, i32 addrspace(1)* undef 85 store volatile i32 %val1, i32 addrspace(1)* undef 86 ret void 87} 88 89; HSA: define void @func_indirect_use_workitem_id_x() #1 { 90define void @func_indirect_use_workitem_id_x() #1 { 91 call void @use_workitem_id_x() 92 ret void 93} 94 95; HSA: define void @kernel_indirect_use_workitem_id_x() #1 { 96define void @kernel_indirect_use_workitem_id_x() #1 { 97 call void @use_workitem_id_x() 98 ret void 99} 100 101; HSA: define void @func_indirect_use_workitem_id_y() #2 { 102define void @func_indirect_use_workitem_id_y() #1 { 103 call void @use_workitem_id_y() 104 ret void 105} 106 107; HSA: define void @func_indirect_use_workitem_id_z() #3 { 108define void @func_indirect_use_workitem_id_z() #1 { 109 call void @use_workitem_id_z() 110 ret void 111} 112 113; HSA: define void @func_indirect_use_workgroup_id_x() #4 { 114define void @func_indirect_use_workgroup_id_x() #1 { 115 call void @use_workgroup_id_x() 116 ret void 117} 118 119; HSA: define void @kernel_indirect_use_workgroup_id_x() #4 { 120define void @kernel_indirect_use_workgroup_id_x() #1 { 121 call void @use_workgroup_id_x() 122 ret void 123} 124 125; HSA: define void @func_indirect_use_workgroup_id_y() #5 { 126define void @func_indirect_use_workgroup_id_y() #1 { 127 call void @use_workgroup_id_y() 128 ret void 129} 130 131; HSA: define void @func_indirect_use_workgroup_id_z() #6 { 132define void @func_indirect_use_workgroup_id_z() #1 { 133 call void @use_workgroup_id_z() 134 ret void 135} 136 137; HSA: define void @func_indirect_indirect_use_workgroup_id_y() #5 { 138define void @func_indirect_indirect_use_workgroup_id_y() #1 { 139 call void @func_indirect_use_workgroup_id_y() 140 ret void 141} 142 143; HSA: define void @indirect_x2_use_workgroup_id_y() #5 { 144define void @indirect_x2_use_workgroup_id_y() #1 { 145 call void @func_indirect_indirect_use_workgroup_id_y() 146 ret void 147} 148 149; HSA: define void @func_indirect_use_dispatch_ptr() #7 { 150define void @func_indirect_use_dispatch_ptr() #1 { 151 call void @use_dispatch_ptr() 152 ret void 153} 154 155; HSA: define void @func_indirect_use_queue_ptr() #8 { 156define void @func_indirect_use_queue_ptr() #1 { 157 call void @use_queue_ptr() 158 ret void 159} 160 161; HSA: define void @func_indirect_use_dispatch_id() #9 { 162define void @func_indirect_use_dispatch_id() #1 { 163 call void @use_dispatch_id() 164 ret void 165} 166 167; HSA: define void @func_indirect_use_workgroup_id_y_workgroup_id_z() #11 { 168define void @func_indirect_use_workgroup_id_y_workgroup_id_z() #1 { 169 call void @func_indirect_use_workgroup_id_y_workgroup_id_z() 170 ret void 171} 172 173; HSA: define void @recursive_use_workitem_id_y() #2 { 174define void @recursive_use_workitem_id_y() #1 { 175 %val = call i32 @llvm.amdgcn.workitem.id.y() 176 store volatile i32 %val, i32 addrspace(1)* undef 177 call void @recursive_use_workitem_id_y() 178 ret void 179} 180 181; HSA: define void @call_recursive_use_workitem_id_y() #2 { 182define void @call_recursive_use_workitem_id_y() #1 { 183 call void @recursive_use_workitem_id_y() 184 ret void 185} 186 187; HSA: define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #8 { 188define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 { 189 %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* 190 store volatile i32 0, i32 addrspace(4)* %stof 191 ret void 192} 193 194; HSA: define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #12 { 195define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #2 { 196 %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* 197 store volatile i32 0, i32 addrspace(4)* %stof 198 ret void 199} 200 201; HSA: define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #13 { 202define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #2 { 203 %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* 204 store volatile i32 0, i32 addrspace(4)* %stof 205 call void @func_indirect_use_queue_ptr() 206 ret void 207} 208 209; HSA: define void @indirect_use_group_to_flat_addrspacecast() #8 { 210define void @indirect_use_group_to_flat_addrspacecast() #1 { 211 call void @use_group_to_flat_addrspacecast(i32 addrspace(3)* null) 212 ret void 213} 214 215; HSA: define void @indirect_use_group_to_flat_addrspacecast_gfx9() #11 { 216define void @indirect_use_group_to_flat_addrspacecast_gfx9() #1 { 217 call void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* null) 218 ret void 219} 220 221; HSA: define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #8 { 222define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #1 { 223 call void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* null) 224 ret void 225} 226 227; HSA: define void @use_kernarg_segment_ptr() #14 { 228define void @use_kernarg_segment_ptr() #1 { 229 %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() 230 store volatile i8 addrspace(4)* %kernarg.segment.ptr, i8 addrspace(4)* addrspace(1)* undef 231 ret void 232} 233 234; HSA: define void @func_indirect_use_kernarg_segment_ptr() #11 { 235define void @func_indirect_use_kernarg_segment_ptr() #1 { 236 call void @use_kernarg_segment_ptr() 237 ret void 238} 239 240; HSA: define amdgpu_kernel void @kern_use_implicitarg_ptr() #15 { 241define amdgpu_kernel void @kern_use_implicitarg_ptr() #1 { 242 %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() 243 store volatile i8 addrspace(4)* %implicitarg.ptr, i8 addrspace(4)* addrspace(1)* undef 244 ret void 245} 246 247; HSA: define void @use_implicitarg_ptr() #16 { 248define void @use_implicitarg_ptr() #1 { 249 %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() 250 store volatile i8 addrspace(4)* %implicitarg.ptr, i8 addrspace(4)* addrspace(1)* undef 251 ret void 252} 253 254; HSA: define void @func_indirect_use_implicitarg_ptr() #16 { 255define void @func_indirect_use_implicitarg_ptr() #1 { 256 call void @use_implicitarg_ptr() 257 ret void 258} 259 260; HSA: declare void @external.func() #17 261declare void @external.func() #3 262 263; HSA: define internal void @defined.func() #17 { 264define internal void @defined.func() #3 { 265 ret void 266} 267 268; HSA: define void @func_call_external() #17 { 269define void @func_call_external() #3 { 270 call void @external.func() 271 ret void 272} 273 274; HSA: define void @func_call_defined() #17 { 275define void @func_call_defined() #3 { 276 call void @defined.func() 277 ret void 278} 279 280; HSA: define void @func_call_asm() #18 { 281define void @func_call_asm() #3 { 282 call void asm sideeffect "", ""() #3 283 ret void 284} 285 286; HSA: define amdgpu_kernel void @kern_call_external() #19 { 287define amdgpu_kernel void @kern_call_external() #3 { 288 call void @external.func() 289 ret void 290} 291 292; HSA: define amdgpu_kernel void @func_kern_defined() #19 { 293define amdgpu_kernel void @func_kern_defined() #3 { 294 call void @defined.func() 295 ret void 296} 297 298; HSA: define i32 @use_dispatch_ptr_ret_type() #20 { 299define i32 @use_dispatch_ptr_ret_type() #1 { 300 %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() 301 store volatile i8 addrspace(4)* %dispatch.ptr, i8 addrspace(4)* addrspace(1)* undef 302 ret i32 0 303} 304 305; HSA: define float @func_indirect_use_dispatch_ptr_constexpr_cast_func() #20 { 306define float @func_indirect_use_dispatch_ptr_constexpr_cast_func() #1 { 307 %f = call float bitcast (i32()* @use_dispatch_ptr_ret_type to float()*)() 308 %fadd = fadd float %f, 1.0 309 ret float %fadd 310} 311 312attributes #0 = { nounwind readnone speculatable } 313attributes #1 = { nounwind "target-cpu"="fiji" } 314attributes #2 = { nounwind "target-cpu"="gfx900" } 315attributes #3 = { nounwind } 316 317; HSA: attributes #0 = { nounwind readnone speculatable willreturn } 318; HSA: attributes #1 = { nounwind "amdgpu-work-item-id-x" "target-cpu"="fiji" "uniform-work-group-size"="false" } 319; HSA: attributes #2 = { nounwind "amdgpu-work-item-id-y" "target-cpu"="fiji" "uniform-work-group-size"="false" } 320; HSA: attributes #3 = { nounwind "amdgpu-work-item-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } 321; HSA: attributes #4 = { nounwind "amdgpu-work-group-id-x" "target-cpu"="fiji" "uniform-work-group-size"="false" } 322; HSA: attributes #5 = { nounwind "amdgpu-work-group-id-y" "target-cpu"="fiji" "uniform-work-group-size"="false" } 323; HSA: attributes #6 = { nounwind "amdgpu-work-group-id-z" "target-cpu"="fiji" "uniform-work-group-size"="false" } 324; HSA: attributes #7 = { nounwind "amdgpu-dispatch-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" } 325; HSA: attributes #8 = { nounwind "amdgpu-queue-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" } 326; HSA: attributes #9 = { nounwind "amdgpu-dispatch-id" "target-cpu"="fiji" "uniform-work-group-size"="false" } 327; HSA: attributes #10 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "target-cpu"="fiji" } 328; HSA: attributes #11 = { nounwind "target-cpu"="fiji" "uniform-work-group-size"="false" } 329; HSA: attributes #12 = { nounwind "target-cpu"="gfx900" "uniform-work-group-size"="false" } 330; HSA: attributes #13 = { nounwind "amdgpu-queue-ptr" "target-cpu"="gfx900" "uniform-work-group-size"="false" } 331; HSA: attributes #14 = { nounwind "amdgpu-kernarg-segment-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" } 332; HSA: attributes #15 = { nounwind "amdgpu-implicitarg-ptr" "target-cpu"="fiji" } 333; HSA: attributes #16 = { nounwind "amdgpu-implicitarg-ptr" "target-cpu"="fiji" "uniform-work-group-size"="false" } 334; HSA: attributes #17 = { nounwind "uniform-work-group-size"="false" } 335; HSA: attributes #18 = { nounwind } 336; HSA: attributes #19 = { nounwind "amdgpu-calls" "uniform-work-group-size"="false" } 337; HSA: attributes #20 = { nounwind "amdgpu-dispatch-ptr" "target-cpu"="fiji" } 338