1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s 3 4define amdgpu_kernel void @eq_t(float %x) { 5; GCN-LABEL: eq_t: 6; GCN: ; %bb.0: 7; GCN-NEXT: s_load_dword s0, s[0:1], 0x24 8; GCN-NEXT: s_waitcnt lgkmcnt(0) 9; GCN-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, 1.0 10; GCN-NEXT: v_cndmask_b32_e64 v0, 2.0, 4.0, s[0:1] 11; GCN-NEXT: flat_store_dword v[0:1], v0 12; GCN-NEXT: s_endpgm 13 %c1 = fcmp olt float %x, 1.0 14 %s1 = select i1 %c1, i32 56789, i32 1 15 %c2 = icmp eq i32 %s1, 56789 16 %s2 = select i1 %c2, float 4.0, float 2.0 17 store float %s2, float* undef, align 4 18 ret void 19} 20 21define amdgpu_kernel void @ne_t(float %x) { 22; GCN-LABEL: ne_t: 23; GCN: ; %bb.0: 24; GCN-NEXT: s_load_dword s0, s[0:1], 0x24 25; GCN-NEXT: s_waitcnt lgkmcnt(0) 26; GCN-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, 1.0 27; GCN-NEXT: v_cndmask_b32_e64 v0, 4.0, 2.0, s[0:1] 28; GCN-NEXT: flat_store_dword v[0:1], v0 29; GCN-NEXT: s_endpgm 30 %c1 = fcmp olt float %x, 1.0 31 %s1 = select i1 %c1, i32 56789, i32 1 32 %c2 = icmp ne i32 %s1, 56789 33 %s2 = select i1 %c2, float 4.0, float 2.0 34 store float %s2, float* undef, align 4 35 ret void 36} 37 38define amdgpu_kernel void @eq_f(float %x) { 39; GCN-LABEL: eq_f: 40; GCN: ; %bb.0: 41; GCN-NEXT: s_load_dword s0, s[0:1], 0x24 42; GCN-NEXT: s_waitcnt lgkmcnt(0) 43; GCN-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, 1.0 44; GCN-NEXT: v_cndmask_b32_e64 v0, 4.0, 2.0, s[0:1] 45; GCN-NEXT: flat_store_dword v[0:1], v0 46; GCN-NEXT: s_endpgm 47 %c1 = fcmp olt float %x, 1.0 48 %s1 = select i1 %c1, i32 1, i32 56789 49 %c2 = icmp eq i32 %s1, 56789 50 %s2 = select i1 %c2, float 4.0, float 2.0 51 store float %s2, float* undef, align 4 52 ret void 53} 54 55define amdgpu_kernel void @ne_f(float %x) { 56; GCN-LABEL: ne_f: 57; GCN: ; %bb.0: 58; GCN-NEXT: s_load_dword s0, s[0:1], 0x24 59; GCN-NEXT: s_waitcnt lgkmcnt(0) 60; GCN-NEXT: v_cmp_lt_f32_e64 s[0:1], s0, 1.0 61; GCN-NEXT: v_cndmask_b32_e64 v0, 2.0, 4.0, s[0:1] 62; GCN-NEXT: flat_store_dword v[0:1], v0 63; GCN-NEXT: s_endpgm 64 %c1 = fcmp olt float %x, 1.0 65 %s1 = select i1 %c1, i32 1, i32 56789 66 %c2 = icmp ne i32 %s1, 56789 67 %s2 = select i1 %c2, float 4.0, float 2.0 68 store float %s2, float* undef, align 4 69 ret void 70} 71 72define amdgpu_kernel void @different_constants(float %x) { 73; GCN-LABEL: different_constants: 74; GCN: ; %bb.0: 75; GCN-NEXT: v_mov_b32_e32 v0, 2.0 76; GCN-NEXT: flat_store_dword v[0:1], v0 77; GCN-NEXT: s_endpgm 78 %c1 = fcmp olt float %x, 1.0 79 %s1 = select i1 %c1, i32 56789, i32 1 80 %c2 = icmp eq i32 %s1, 5678 81 %s2 = select i1 %c2, float 4.0, float 2.0 82 store float %s2, float* undef, align 4 83 ret void 84} 85