1; RUN: llc -mtriple=amdgcn--amdpal -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 2 3define amdgpu_hs void @foo(i32 inreg %arg, <4 x i32> inreg %buffer) { 4entry: 5 br label %work 6 7bb42: 8 br label %bb602 9 10bb602: 11 %tmp603 = phi i32 [ 0, %bb42 ], [ 1, %work ] 12 %tmp607 = icmp eq i32 %tmp603, %tmp1196 13 br i1 %tmp607, label %bb49, label %bb54 14 15bb49: 16 call void @llvm.amdgcn.raw.tbuffer.store.f32(float 1.0, <4 x i32> %buffer, i32 4, i32 1, i32 116, i32 1) 17 ret void 18 19bb54: 20 ret void 21 22work: 23; GCN: s_not_b64 exec, exec 24; GCN: v_mov_b32_e32 v[[tmp1189:[0-9]+]], 1 25; GCN: s_not_b64 exec, exec 26 %tmp1189 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 4, i32 1) 27 28; GCN: s_or_saveexec_b64 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, -1 29; GCN: v_lshlrev_b32_e32 v[[tmp1191:[0-9]+]], 2, v[[tmp1189]] 30 %tmp1191 = mul i32 %tmp1189, 4 31 32; GCN: s_mov_b64 exec, s{{\[}}[[LO]]:[[HI]]{{\]}} 33 %tmp1196 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp1191) 34 35 %tmp34 = icmp eq i32 %arg, 0 36 br i1 %tmp34, label %bb602, label %bb42 37} 38 39declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) #0 40declare i32 @llvm.amdgcn.wwm.i32(i32) #1 41declare void @llvm.amdgcn.raw.tbuffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg, i32 immarg) #2 42 43attributes #0 = { convergent nounwind readnone willreturn } 44attributes #1 = { convergent nounwind readnone speculatable willreturn } 45attributes #2 = { nounwind willreturn writeonly } 46