1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s 3; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s 4 5; GCN-LABEL: {{^}}test_fmax3_olt_0_f32: 6; GCN: buffer_load_dword [[REGC:v[0-9]+]] 7; GCN: buffer_load_dword [[REGB:v[0-9]+]] 8; GCN: buffer_load_dword [[REGA:v[0-9]+]] 9; GCN: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]] 10; GCN: buffer_store_dword [[RESULT]], 11; GCN: s_endpgm 12define amdgpu_kernel void @test_fmax3_olt_0_f32(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #0 { 13 %a = load volatile float, float addrspace(1)* %aptr, align 4 14 %b = load volatile float, float addrspace(1)* %bptr, align 4 15 %c = load volatile float, float addrspace(1)* %cptr, align 4 16 %f0 = call float @llvm.maxnum.f32(float %a, float %b) 17 %f1 = call float @llvm.maxnum.f32(float %f0, float %c) 18 store float %f1, float addrspace(1)* %out, align 4 19 ret void 20} 21 22; Commute operand of second fmax 23; GCN-LABEL: {{^}}test_fmax3_olt_1_f32: 24; GCN: buffer_load_dword [[REGB:v[0-9]+]] 25; GCN: buffer_load_dword [[REGA:v[0-9]+]] 26; GCN: buffer_load_dword [[REGC:v[0-9]+]] 27; GCN: v_max3_f32 [[RESULT:v[0-9]+]], [[REGC]], [[REGB]], [[REGA]] 28; GCN: buffer_store_dword [[RESULT]], 29; GCN: s_endpgm 30define amdgpu_kernel void @test_fmax3_olt_1_f32(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #0 { 31 %a = load volatile float, float addrspace(1)* %aptr, align 4 32 %b = load volatile float, float addrspace(1)* %bptr, align 4 33 %c = load volatile float, float addrspace(1)* %cptr, align 4 34 %f0 = call float @llvm.maxnum.f32(float %a, float %b) 35 %f1 = call float @llvm.maxnum.f32(float %c, float %f0) 36 store float %f1, float addrspace(1)* %out, align 4 37 ret void 38} 39 40; GCN-LABEL: {{^}}test_fmax3_olt_0_f16: 41; GCN: buffer_load_ushort [[REGA:v[0-9]+]] 42; GCN: buffer_load_ushort [[REGB:v[0-9]+]] 43; GCN: buffer_load_ushort [[REGC:v[0-9]+]] 44 45; SI-DAG: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], [[REGA]] 46; SI-DAG: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], [[REGB]] 47; SI-DAG: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], [[REGC]] 48; SI: v_max3_f32 [[RESULT_F32:v[0-9]+]], [[CVT_A]], [[CVT_B]], [[CVT_C]] 49; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT_F32]] 50 51; VI-DAG: v_max_f16_e32 [[QUIET_A:v[0-9]+]], [[REGA]], [[REGA]] 52; VI-DAG: v_max_f16_e32 [[QUIET_B:v[0-9]+]], [[REGB]], [[REGB]] 53; VI: v_max_f16_e32 [[MAX0:v[0-9]+]], [[QUIET_A]], [[QUIET_B]] 54; VI: v_max_f16_e32 [[QUIET_C:v[0-9]+]], [[REGC]], [[REGC]] 55; VI: v_max_f16_e32 [[RESULT:v[0-9]+]], [[MAX0]], [[QUIET_C]] 56 57; GFX9: v_max3_f16 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], [[REGC]] 58; GCN: buffer_store_short [[RESULT]], 59define amdgpu_kernel void @test_fmax3_olt_0_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 { 60 %a = load volatile half, half addrspace(1)* %aptr, align 2 61 %b = load volatile half, half addrspace(1)* %bptr, align 2 62 %c = load volatile half, half addrspace(1)* %cptr, align 2 63 %f0 = call half @llvm.maxnum.f16(half %a, half %b) 64 %f1 = call half @llvm.maxnum.f16(half %f0, half %c) 65 store half %f1, half addrspace(1)* %out, align 2 66 ret void 67} 68 69; Commute operand of second fmax 70; GCN-LABEL: {{^}}test_fmax3_olt_1_f16: 71; GCN: buffer_load_ushort [[REGA:v[0-9]+]] 72; GCN: buffer_load_ushort [[REGB:v[0-9]+]] 73; GCN: buffer_load_ushort [[REGC:v[0-9]+]] 74 75; SI-DAG: v_cvt_f32_f16_e32 [[CVT_A:v[0-9]+]], [[REGA]] 76; SI-DAG: v_cvt_f32_f16_e32 [[CVT_B:v[0-9]+]], [[REGB]] 77; SI-DAG: v_cvt_f32_f16_e32 [[CVT_C:v[0-9]+]], [[REGC]] 78; SI: v_max3_f32 [[RESULT_F32:v[0-9]+]], [[CVT_C]], [[CVT_A]], [[CVT_B]] 79; SI: v_cvt_f16_f32_e32 [[RESULT:v[0-9]+]], [[RESULT_F32]] 80 81; VI-DAG: v_max_f16_e32 [[QUIET_A:v[0-9]+]], [[REGA]], [[REGA]] 82; VI-DAG: v_max_f16_e32 [[QUIET_B:v[0-9]+]], [[REGB]], [[REGB]] 83; VI: v_max_f16_e32 [[MAX0:v[0-9]+]], [[QUIET_A]], [[QUIET_B]] 84; VI: v_max_f16_e32 [[QUIET_C:v[0-9]+]], [[REGC]], [[REGC]] 85; VI: v_max_f16_e32 [[RESULT:v[0-9]+]], [[QUIET_C]], [[MAX0]] 86 87; GFX9: v_max3_f16 [[RESULT:v[0-9]+]], [[REGC]], [[REGA]], [[REGB]] 88; GCN: buffer_store_short [[RESULT]], 89define amdgpu_kernel void @test_fmax3_olt_1_f16(half addrspace(1)* %out, half addrspace(1)* %aptr, half addrspace(1)* %bptr, half addrspace(1)* %cptr) #0 { 90 %a = load volatile half, half addrspace(1)* %aptr, align 2 91 %b = load volatile half, half addrspace(1)* %bptr, align 2 92 %c = load volatile half, half addrspace(1)* %cptr, align 2 93 %f0 = call half @llvm.maxnum.f16(half %a, half %b) 94 %f1 = call half @llvm.maxnum.f16(half %c, half %f0) 95 store half %f1, half addrspace(1)* %out, align 2 96 ret void 97} 98 99; Checks whether the test passes; performMinMaxCombine() should not optimize vector patterns of max3 100; since there are no pack instructions for fmax3. 101; GCN-LABEL: {{^}}no_fmax3_v2f16: 102 103; SI: v_cvt_f16_f32_e32 104; SI: v_max_f32_e32 105; SI-NEXT: v_max_f32_e32 106; SI-NEXT: v_max3_f32 107; SI-NEXT: v_max3_f32 108 109; VI: s_waitcnt 110; VI-NEXT: v_max_f16_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 111; VI-NEXT: v_max_f16_e32 v0, v0, v1 112; VI-NEXT: v_max_f16_sdwa v1, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 113; VI-NEXT: v_max_f16_e32 v0, v2, v0 114; VI-NEXT: v_max_f16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 115; VI-NEXT: v_max_f16_e32 v0, v0, v3 116; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 117; VI-NEXT: s_setpc_b64 118 119; GFX9: s_waitcnt 120; GFX9-NEXT: v_pk_max_f16 121; GFX9-NEXT: v_pk_max_f16 122; GFX9-NEXT: v_pk_max_f16 123define <2 x half> @no_fmax3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) #2 { 124entry: 125 %max = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b) 126 %max1 = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %c, <2 x half> %max) 127 %res = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %max1, <2 x half> %d) 128 ret <2 x half> %res 129} 130 131declare i32 @llvm.amdgcn.workitem.id.x() #1 132declare float @llvm.maxnum.f32(float, float) #1 133declare half @llvm.maxnum.f16(half, half) #1 134declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>) 135 136attributes #0 = { nounwind } 137attributes #1 = { nounwind readnone speculatable } 138attributes #2 = { nounwind "no-nans-fp-math"="true" } 139