1;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=VERDE %s 2;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s 3 4;CHECK-LABEL: {{^}}buffer_store: 5;CHECK-NOT: s_waitcnt 6;CHECK: buffer_store_format_xyzw v[0:3], off, s[0:3], 0 7;CHECK: buffer_store_format_xyzw v[4:7], off, s[0:3], 0 glc 8;CHECK: buffer_store_format_xyzw v[8:11], off, s[0:3], 0 slc 9define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) { 10main_body: 11 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i1 0, i1 0) 12 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i1 1, i1 0) 13 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i1 0, i1 1) 14 ret void 15} 16 17;CHECK-LABEL: {{^}}buffer_store_immoffs: 18;CHECK-NOT: s_waitcnt 19;CHECK: buffer_store_format_xyzw v[0:3], off, s[0:3], 0 offset:42 20define amdgpu_ps void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) { 21main_body: 22 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0) 23 ret void 24} 25 26;CHECK-LABEL: {{^}}buffer_store_idx: 27;CHECK-NOT: s_waitcnt 28;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen 29define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) { 30main_body: 31 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0) 32 ret void 33} 34 35;CHECK-LABEL: {{^}}buffer_store_ofs: 36;CHECK-NOT: s_waitcnt 37;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 offen 38define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) { 39main_body: 40 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i1 0, i1 0) 41 ret void 42} 43 44;CHECK-LABEL: {{^}}buffer_store_both: 45;CHECK-NOT: s_waitcnt 46;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen 47define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) { 48main_body: 49 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i1 0, i1 0) 50 ret void 51} 52 53;CHECK-LABEL: {{^}}buffer_store_both_reversed: 54;CHECK: v_mov_b32_e32 v6, v4 55;CHECK-NOT: s_waitcnt 56;CHECK: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen 57define amdgpu_ps void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) { 58main_body: 59 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i1 0, i1 0) 60 ret void 61} 62 63; Ideally, the register allocator would avoid the wait here 64; 65;CHECK-LABEL: {{^}}buffer_store_wait: 66;CHECK-NOT: s_waitcnt 67;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen 68;VERDE: s_waitcnt expcnt(0) 69;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen 70;CHECK: s_waitcnt vmcnt(0) 71;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen 72define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) { 73main_body: 74 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0) 75 %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %3, i32 0, i1 0, i1 0) 76 call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i1 0, i1 0) 77 ret void 78} 79 80;CHECK-LABEL: {{^}}buffer_store_x1: 81;CHECK-NOT: s_waitcnt 82;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 idxen 83define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %index) { 84main_body: 85 call void @llvm.amdgcn.buffer.store.format.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) 86 ret void 87} 88 89;CHECK-LABEL: {{^}}buffer_store_x2: 90;CHECK-NOT: s_waitcnt 91;CHECK: buffer_store_format_xy v[0:1], v2, s[0:3], 0 idxen 92define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %index) { 93main_body: 94 call void @llvm.amdgcn.buffer.store.format.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) 95 ret void 96} 97 98declare void @llvm.amdgcn.buffer.store.format.f32(float, <4 x i32>, i32, i32, i1, i1) #0 99declare void @llvm.amdgcn.buffer.store.format.v2f32(<2 x float>, <4 x i32>, i32, i32, i1, i1) #0 100declare void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #0 101declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1 102 103attributes #0 = { nounwind } 104attributes #1 = { nounwind readonly } 105