1; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=UNPACKED %s 2; RUN: llc < %s -march=amdgcn -mcpu=gfx810 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s 3; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=PACKED %s 4 5; GCN-LABEL: {{^}}buffer_load_format_d16_x: 6; GCN: buffer_load_format_d16_x v{{[0-9]+}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen 7define amdgpu_ps half @buffer_load_format_d16_x(<4 x i32> inreg %rsrc) { 8main_body: 9 %data = call half @llvm.amdgcn.struct.buffer.load.format.f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) 10 ret half %data 11} 12 13; GCN-LABEL: {{^}}buffer_load_format_d16_xy: 14; UNPACKED: buffer_load_format_d16_xy v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen 15; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] 16 17; PACKED: buffer_load_format_d16_xy v[[FULL:[0-9]+]], {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen 18; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[FULL]] 19define amdgpu_ps half @buffer_load_format_d16_xy(<4 x i32> inreg %rsrc) { 20main_body: 21 %data = call <2 x half> @llvm.amdgcn.struct.buffer.load.format.v2f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) 22 %elt = extractelement <2 x half> %data, i32 1 23 ret half %elt 24} 25 26; GCN-LABEL: {{^}}buffer_load_format_d16_xyz: 27; UNPACKED: buffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen 28; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] 29 30; PACKED: buffer_load_format_d16_xyz v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen 31; PACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] 32define amdgpu_ps half @buffer_load_format_d16_xyz(<4 x i32> inreg %rsrc) { 33main_body: 34 %data = call <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) 35 %elt = extractelement <3 x half> %data, i32 2 36 ret half %elt 37} 38 39; GCN-LABEL: {{^}}buffer_load_format_d16_xyzw: 40; UNPACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen 41; UNPACKED: v_mov_b32_e32 v{{[0-9]+}}, v[[HI]] 42 43; PACKED: buffer_load_format_d16_xyzw v{{\[}}{{[0-9]+}}:[[HI:[0-9]+]]{{\]}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen 44; PACKED: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v[[HI]] 45define amdgpu_ps half @buffer_load_format_d16_xyzw(<4 x i32> inreg %rsrc) { 46main_body: 47 %data = call <4 x half> @llvm.amdgcn.struct.buffer.load.format.v4f16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) 48 %elt = extractelement <4 x half> %data, i32 3 49 ret half %elt 50} 51 52; GCN-LABEL: {{^}}buffer_load_format_i16_x: 53; GCN: buffer_load_format_d16_x v{{[0-9]+}}, {{v[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 idxen 54define amdgpu_ps half @buffer_load_format_i16_x(<4 x i32> inreg %rsrc) { 55main_body: 56 %data = call i16 @llvm.amdgcn.struct.buffer.load.format.i16(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) 57 %fdata = bitcast i16 %data to half 58 ret half %fdata 59} 60 61declare half @llvm.amdgcn.struct.buffer.load.format.f16(<4 x i32>, i32, i32, i32, i32) 62declare <2 x half> @llvm.amdgcn.struct.buffer.load.format.v2f16(<4 x i32>, i32, i32, i32, i32) 63declare <3 x half> @llvm.amdgcn.struct.buffer.load.format.v3f16(<4 x i32>, i32, i32, i32, i32) 64declare <4 x half> @llvm.amdgcn.struct.buffer.load.format.v4f16(<4 x i32>, i32, i32, i32, i32) 65declare i16 @llvm.amdgcn.struct.buffer.load.format.i16(<4 x i32>, i32, i32, i32, i32) 66