1;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=VERDE %s 2;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s 3 4;CHECK-LABEL: {{^}}buffer_store: 5;CHECK-NOT: s_waitcnt 6;CHECK: buffer_store_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen 7;CHECK: buffer_store_dwordx4 v[4:7], {{v[0-9]+}}, s[0:3], 0 idxen glc 8;CHECK: buffer_store_dwordx4 v[8:11], {{v[0-9]+}}, s[0:3], 0 idxen slc 9define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) { 10main_body: 11 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i32 0, i32 0) 12 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i32 0, i32 1) 13 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i32 0, i32 2) 14 ret void 15} 16 17;CHECK-LABEL: {{^}}buffer_store_immoffs: 18;CHECK-NOT: s_waitcnt 19;CHECK: buffer_store_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen offset:42 20define amdgpu_ps void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) { 21main_body: 22 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i32 0, i32 0) 23 ret void 24} 25 26;CHECK-LABEL: {{^}}buffer_store_idx: 27;CHECK-NOT: s_waitcnt 28;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen 29define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) { 30main_body: 31 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0, i32 0) 32 ret void 33} 34 35;CHECK-LABEL: {{^}}buffer_store_ofs: 36;CHECK-NOT: s_waitcnt 37;CHECK: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen 38define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) { 39main_body: 40 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i32 0, i32 0) 41 ret void 42} 43 44;CHECK-LABEL: {{^}}buffer_store_both: 45;CHECK-NOT: s_waitcnt 46;CHECK: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen 47define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) { 48main_body: 49 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i32 0, i32 0) 50 ret void 51} 52 53;CHECK-LABEL: {{^}}buffer_store_both_reversed: 54;CHECK: v_mov_b32_e32 v6, v4 55;CHECK-NOT: s_waitcnt 56;CHECK: buffer_store_dwordx4 v[0:3], v[5:6], s[0:3], 0 idxen offen 57define amdgpu_ps void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) { 58main_body: 59 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i32 0, i32 0) 60 ret void 61} 62 63; Ideally, the register allocator would avoid the wait here 64; 65;CHECK-LABEL: {{^}}buffer_store_wait: 66;CHECK-NOT: s_waitcnt 67;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen 68;VERDE: s_waitcnt expcnt(0) 69;CHECK: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen 70;CHECK: s_waitcnt vmcnt(0) 71;CHECK: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen 72define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) { 73main_body: 74 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i32 0, i32 0) 75 %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 %3, i32 0, i32 0, i32 0) 76 call void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i32 0, i32 0) 77 ret void 78} 79 80;CHECK-LABEL: {{^}}buffer_store_x1: 81;CHECK-NOT: s_waitcnt 82;CHECK: buffer_store_dword v0, v1, s[0:3], 0 idxen 83define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %index) { 84main_body: 85 call void @llvm.amdgcn.struct.buffer.store.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0) 86 ret void 87} 88 89;CHECK-LABEL: {{^}}buffer_store_x2: 90;CHECK-NOT: s_waitcnt 91;CHECK: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen 92define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %index) #0 { 93main_body: 94 call void @llvm.amdgcn.struct.buffer.store.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0) 95 ret void 96} 97 98;CHECK-LABEL: {{^}}buffer_store_int: 99;CHECK-NOT: s_waitcnt 100;CHECK: buffer_store_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen 101;CHECK: buffer_store_dwordx2 v[4:5], {{v[0-9]+}}, s[0:3], 0 idxen glc 102;CHECK: buffer_store_dword v6, {{v[0-9]+}}, s[0:3], 0 idxen slc 103define amdgpu_ps void @buffer_store_int(<4 x i32> inreg, <4 x i32>, <2 x i32>, i32) { 104main_body: 105 call void @llvm.amdgcn.struct.buffer.store.v4i32(<4 x i32> %1, <4 x i32> %0, i32 0, i32 0, i32 0, i32 0) 106 call void @llvm.amdgcn.struct.buffer.store.v2i32(<2 x i32> %2, <4 x i32> %0, i32 0, i32 0, i32 0, i32 1) 107 call void @llvm.amdgcn.struct.buffer.store.i32(i32 %3, <4 x i32> %0, i32 0, i32 0, i32 0, i32 2) 108 ret void 109} 110 111;CHECK-LABEL: {{^}}struct_buffer_store_byte: 112;CHECK-NEXT: %bb. 113;CHECK-NEXT: v_cvt_u32_f32_e32 v{{[0-9]}}, v{{[0-9]}} 114;CHECK-NEXT: buffer_store_byte v{{[0-9]}}, v{{[0-9]}}, s[0:3], 0 idxen 115;CHECK-NEXT: s_endpgm 116define amdgpu_ps void @struct_buffer_store_byte(<4 x i32> inreg %rsrc, float %v1, i32 %index) { 117main_body: 118 %v2 = fptoui float %v1 to i32 119 %v3 = trunc i32 %v2 to i8 120 call void @llvm.amdgcn.struct.buffer.store.i8(i8 %v3, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0) 121 ret void 122} 123 124;CHECK-LABEL: {{^}}struct_buffer_store_f16: 125;CHECK-NEXT: %bb. 126;CHECK-NEXT: v_cvt_f16_f32_e32 v{{[0-9]}}, v{{[0-9]}} 127;CHECK-NEXT: buffer_store_short v{{[0-9]}}, v{{[0-9]}}, s[0:3], 0 idxen 128;CHECK-NEXT: s_endpgm 129define amdgpu_ps void @struct_buffer_store_f16(<4 x i32> inreg %rsrc, float %v1, i32 %index) { 130 %v2 = fptrunc float %v1 to half 131 call void @llvm.amdgcn.struct.buffer.store.f16(half %v2, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0) 132 ret void 133} 134 135;CHECK-LABEL: {{^}}struct_buffer_store_v2f16: 136;CHECK-NEXT: %bb. 137;CHECK: buffer_store_dword v0, {{v[0-9]+}}, s[0:3], 0 idxen 138define amdgpu_ps void @struct_buffer_store_v2f16(<4 x i32> inreg %rsrc, <2 x half> %v1, i32 %index) { 139 call void @llvm.amdgcn.struct.buffer.store.v2f16(<2 x half> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0) 140 ret void 141} 142 143;CHECK-LABEL: {{^}}struct_buffer_store_v4f16: 144;CHECK-NEXT: %bb. 145;CHECK: buffer_store_dwordx2 v[0:1], {{v[0-9]+}}, s[0:3], 0 idxen 146define amdgpu_ps void @struct_buffer_store_v4f16(<4 x i32> inreg %rsrc, <4 x half> %v1, i32 %index) { 147 call void @llvm.amdgcn.struct.buffer.store.v4f16(<4 x half> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0) 148 ret void 149} 150 151;CHECK-LABEL: {{^}}struct_buffer_store_i16: 152;CHECK-NEXT: %bb. 153;CHECK-NEXT: v_cvt_u32_f32_e32 v{{[0-9]}}, v{{[0-9]}} 154;CHECK-NEXT: buffer_store_short v{{[0-9]}}, v{{[0-9]}}, s[0:3], 0 idxen 155;CHECK-NEXT: s_endpgm 156define amdgpu_ps void @struct_buffer_store_i16(<4 x i32> inreg %rsrc, float %v1, i32 %index) { 157main_body: 158 %v2 = fptoui float %v1 to i32 159 %v3 = trunc i32 %v2 to i16 160 call void @llvm.amdgcn.struct.buffer.store.i16(i16 %v3, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0) 161 ret void 162} 163 164;CHECK-LABEL: {{^}}struct_buffer_store_vif16: 165;CHECK-NEXT: %bb. 166;CHECK: buffer_store_dword v0, {{v[0-9]+}}, s[0:3], 0 idxen 167define amdgpu_ps void @struct_buffer_store_vif16(<4 x i32> inreg %rsrc, <2 x i16> %v1, i32 %index) { 168 call void @llvm.amdgcn.struct.buffer.store.v2i16(<2 x i16> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0) 169 ret void 170} 171 172;CHECK-LABEL: {{^}}struct_buffer_store_v4i16: 173;CHECK-NEXT: %bb. 174;CHECK: buffer_store_dwordx2 v[0:1], {{v[0-9]+}}, s[0:3], 0 idxen 175define amdgpu_ps void @struct_buffer_store_v4i16(<4 x i32> inreg %rsrc, <4 x i16> %v1, i32 %index) { 176 call void @llvm.amdgcn.struct.buffer.store.v4i16(<4 x i16> %v1, <4 x i32> %rsrc, i32 %index, i32 0, i32 0, i32 0) 177 ret void 178} 179 180declare void @llvm.amdgcn.struct.buffer.store.f32(float, <4 x i32>, i32, i32, i32, i32) #0 181declare void @llvm.amdgcn.struct.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i32, i32) #0 182declare void @llvm.amdgcn.struct.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32, i32) #0 183declare void @llvm.amdgcn.struct.buffer.store.i32(i32, <4 x i32>, i32, i32, i32, i32) #0 184declare void @llvm.amdgcn.struct.buffer.store.v2i32(<2 x i32>, <4 x i32>, i32, i32, i32, i32) #0 185declare void @llvm.amdgcn.struct.buffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32) #0 186declare <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32>, i32, i32, i32, i32) #1 187declare void @llvm.amdgcn.struct.buffer.store.i8(i8, <4 x i32>, i32, i32, i32, i32) #0 188declare void @llvm.amdgcn.struct.buffer.store.i16(i16, <4 x i32>, i32, i32, i32, i32) #0 189declare void @llvm.amdgcn.struct.buffer.store.v2i16(<2 x i16>, <4 x i32>, i32, i32, i32, i32) #0 190declare void @llvm.amdgcn.struct.buffer.store.v4i16(<4 x i16>, <4 x i32>, i32, i32, i32, i32) #0 191declare void @llvm.amdgcn.struct.buffer.store.f16(half, <4 x i32>, i32, i32, i32, i32) #0 192declare void @llvm.amdgcn.struct.buffer.store.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32) #0 193declare void @llvm.amdgcn.struct.buffer.store.v4f16(<4 x half>, <4 x i32>, i32, i32, i32, i32) #0 194 195 196attributes #0 = { nounwind } 197attributes #1 = { nounwind readonly } 198