1; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX8-OPT,GCN-OPT %s 2; RUN: llc -march=amdgcn -mcpu=tonga -O0 -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX8-NOOPT %s 3; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10,GCN-OPT %s 4 5; GCN-LABEL: {{^}}dpp_test: 6; GCN: v_mov_b32_e32 [[DST:v[0-9]+]], s{{[0-9]+}} 7; GCN: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}} 8; GFX8: s_nop 1 9; GCN: v_mov_b32_dpp [[DST]], [[SRC]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} 10define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in1, i32 %in2) { 11 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 0) #0 12 store i32 %tmp0, i32 addrspace(1)* %out 13 ret void 14} 15 16; GCN-LABEL: {{^}}dpp_test_bc: 17; GCN: v_mov_b32_e32 [[DST:v[0-9]+]], s{{[0-9]+}} 18; GCN: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}} 19; GFX8: s_nop 1 20; GCN: v_mov_b32_dpp [[DST]], [[SRC]] quad_perm:[2,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0{{$}} 21define amdgpu_kernel void @dpp_test_bc(i32 addrspace(1)* %out, i32 %in1, i32 %in2) { 22 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 2, i32 1, i32 1, i1 1) #0 23 store i32 %tmp0, i32 addrspace(1)* %out 24 ret void 25} 26 27 28; GCN-LABEL: {{^}}dpp_test1: 29; GFX10: v_add_nc_u32_e32 [[REG:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}} 30; GFX8-OPT: v_add_u32_e32 [[REG:v[0-9]+]], vcc, v{{[0-9]+}}, v{{[0-9]+}} 31; GFX8-NOOPT: v_add_u32_e64 [[REG:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{[0-9]+}} 32; GFX8-NOOPT: v_mov_b32_e32 v{{[0-9]+}}, 0 33; GFX8: s_nop 1 34; GFX8-NEXT: v_mov_b32_dpp {{v[0-9]+}}, [[REG]] quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf 35@0 = internal unnamed_addr addrspace(3) global [448 x i32] undef, align 4 36define weak_odr amdgpu_kernel void @dpp_test1(i32* %arg) local_unnamed_addr { 37bb: 38 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() 39 %tmp1 = zext i32 %tmp to i64 40 %tmp2 = getelementptr inbounds [448 x i32], [448 x i32] addrspace(3)* @0, i32 0, i32 %tmp 41 %tmp3 = load i32, i32 addrspace(3)* %tmp2, align 4 42 fence syncscope("workgroup-one-as") release 43 tail call void @llvm.amdgcn.s.barrier() 44 fence syncscope("workgroup-one-as") acquire 45 %tmp4 = add nsw i32 %tmp3, %tmp3 46 %tmp5 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp4, i32 177, i32 15, i32 15, i1 zeroext false) 47 %tmp6 = add nsw i32 %tmp5, %tmp4 48 %tmp7 = getelementptr inbounds i32, i32* %arg, i64 %tmp1 49 store i32 %tmp6, i32* %tmp7, align 4 50 ret void 51} 52 53; GCN-LABEL: {{^}}update_dpp64_test: 54; GCN: load_dwordx2 v{{\[}}[[SRC_LO:[0-9]+]]:[[SRC_HI:[0-9]+]]] 55; GCN-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} 56; GCN-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} 57define amdgpu_kernel void @update_dpp64_test(i64 addrspace(1)* %arg, i64 %in1, i64 %in2) { 58 %id = tail call i32 @llvm.amdgcn.workitem.id.x() 59 %gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id 60 %load = load i64, i64 addrspace(1)* %gep 61 %tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 1, i32 1, i32 1, i1 0) #0 62 store i64 %tmp0, i64 addrspace(1)* %gep 63 ret void 64} 65 66; GCN-LABEL: {{^}}update_dpp64_imm_old_test: 67; GCN-OPT-DAG: v_mov_b32_e32 v[[OLD_LO:[0-9]+]], 0x3afaedd9 68; GCN-OPT-DAG: v_mov_b32_e32 v[[OLD_HI:[0-9]+]], 0x7047 69; GFX8-NOOPT-DAG: s_mov_b32 s[[SOLD_LO:[0-9]+]], 0x3afaedd9 70; GFX8-NOOPT-DAG: s_movk_i32 s[[SOLD_HI:[0-9]+]], 0x7047 71; GCN-DAG: load_dwordx2 v{{\[}}[[SRC_LO:[0-9]+]]:[[SRC_HI:[0-9]+]]] 72; GCN-OPT-DAG: v_mov_b32_dpp v[[OLD_LO]], v[[SRC_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} 73; GCN-OPT-DAG: v_mov_b32_dpp v[[OLD_HI]], v[[SRC_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} 74; GCN-NOOPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} 75; GCN-NOOPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} 76define amdgpu_kernel void @update_dpp64_imm_old_test(i64 addrspace(1)* %arg, i64 %in2) { 77 %id = tail call i32 @llvm.amdgcn.workitem.id.x() 78 %gep = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %id 79 %load = load i64, i64 addrspace(1)* %gep 80 %tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 123451234512345, i64 %load, i32 1, i32 1, i32 1, i1 0) #0 81 store i64 %tmp0, i64 addrspace(1)* %gep 82 ret void 83} 84 85; GCN-LABEL: {{^}}update_dpp64_imm_src_test: 86; GCN-OPT-DAG: v_mov_b32_e32 v[[OLD_LO:[0-9]+]], 0x3afaedd9 87; GCN-OPT-DAG: v_mov_b32_e32 v[[OLD_HI:[0-9]+]], 0x7047 88; GFX8-NOOPT-DAG: s_mov_b32 s[[SOLD_LO:[0-9]+]], 0x3afaedd9 89; GFX8-NOOPT-DAG: s_movk_i32 s[[SOLD_HI:[0-9]+]], 0x7047 90; GCN-OPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[OLD_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} 91; GCN-OPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[OLD_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} 92; GCN-NOOPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_LO]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} 93; GCN-NOOPT-DAG: v_mov_b32_dpp v{{[0-9]+}}, v[[SRC_HI]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}} 94define amdgpu_kernel void @update_dpp64_imm_src_test(i64 addrspace(1)* %out, i64 %in1) { 95 %tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 123451234512345, i32 1, i32 1, i32 1, i1 0) #0 96 store i64 %tmp0, i64 addrspace(1)* %out 97 ret void 98} 99 100declare i32 @llvm.amdgcn.workitem.id.x() 101declare void @llvm.amdgcn.s.barrier() 102declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #0 103declare i64 @llvm.amdgcn.update.dpp.i64(i64, i64, i32, i32, i32, i1) #0 104 105attributes #0 = { nounwind readnone convergent } 106