1; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX600 %s 2; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX700 %s 3; RUN: llc -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX801 %s 4; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX900 %s 5 6; GCN-LABEL: {{^}}scalar_nand_i32_one_use 7; GCN: s_nand_b32 8define amdgpu_kernel void @scalar_nand_i32_one_use( 9 i32 addrspace(1)* %r0, i32 %a, i32 %b) { 10entry: 11 %and = and i32 %a, %b 12 %r0.val = xor i32 %and, -1 13 store i32 %r0.val, i32 addrspace(1)* %r0 14 ret void 15} 16 17; GCN-LABEL: {{^}}scalar_nand_i32_mul_use 18; GCN-NOT: s_nand_b32 19; GCN: s_and_b32 20; GCN: s_not_b32 21; GCN: s_add_i32 22define amdgpu_kernel void @scalar_nand_i32_mul_use( 23 i32 addrspace(1)* %r0, i32 addrspace(1)* %r1, i32 %a, i32 %b) { 24entry: 25 %and = and i32 %a, %b 26 %r0.val = xor i32 %and, -1 27 %r1.val = add i32 %and, %a 28 store i32 %r0.val, i32 addrspace(1)* %r0 29 store i32 %r1.val, i32 addrspace(1)* %r1 30 ret void 31} 32 33; GCN-LABEL: {{^}}scalar_nand_i64_one_use 34; GCN: s_nand_b64 35define amdgpu_kernel void @scalar_nand_i64_one_use( 36 i64 addrspace(1)* %r0, i64 %a, i64 %b) { 37entry: 38 %and = and i64 %a, %b 39 %r0.val = xor i64 %and, -1 40 store i64 %r0.val, i64 addrspace(1)* %r0 41 ret void 42} 43 44; GCN-LABEL: {{^}}scalar_nand_i64_mul_use 45; GCN-NOT: s_nand_b64 46; GCN: s_and_b64 47; GCN: s_not_b64 48; GCN: s_add_u32 49; GCN: s_addc_u32 50define amdgpu_kernel void @scalar_nand_i64_mul_use( 51 i64 addrspace(1)* %r0, i64 addrspace(1)* %r1, i64 %a, i64 %b) { 52entry: 53 %and = and i64 %a, %b 54 %r0.val = xor i64 %and, -1 55 %r1.val = add i64 %and, %a 56 store i64 %r0.val, i64 addrspace(1)* %r0 57 store i64 %r1.val, i64 addrspace(1)* %r1 58 ret void 59} 60 61; GCN-LABEL: {{^}}vector_nand_i32_one_use 62; GCN-NOT: s_nand_b32 63; GCN: v_and_b32 64; GCN: v_not_b32 65define i32 @vector_nand_i32_one_use(i32 %a, i32 %b) { 66entry: 67 %and = and i32 %a, %b 68 %r = xor i32 %and, -1 69 ret i32 %r 70} 71 72; GCN-LABEL: {{^}}vector_nand_i64_one_use 73; GCN-NOT: s_nand_b64 74; GCN: v_and_b32 75; GCN: v_and_b32 76; GCN: v_not_b32 77; GCN: v_not_b32 78define i64 @vector_nand_i64_one_use(i64 %a, i64 %b) { 79entry: 80 %and = and i64 %a, %b 81 %r = xor i64 %and, -1 82 ret i64 %r 83} 84