1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass=si-lower-sgpr-spills -o - %s | FileCheck %s 3# 4# Check for liveness errors when spilling partially defined super registers. 5 6--- 7name: sgpr_spill_s64_undef_high32 8tracksRegLiveness: true 9machineFunctionInfo: 10 isEntryFunction: true 11 hasSpilledSGPRs: true 12 scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' 13 stackPtrOffsetReg: '$sgpr32' 14 15stack: 16 - { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill } 17 18body: | 19 bb.0: 20 liveins: $sgpr4 21 22 ; CHECK-LABEL: name: sgpr_spill_s64_undef_high32 23 ; CHECK: liveins: $sgpr4, $vgpr0 24 ; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr4, 0, undef $vgpr0, implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr5 25 ; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr5, 1, $vgpr0, implicit $sgpr4_sgpr5 26 SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 8 into %stack.0, align 4, addrspace 5) 27 28... 29 30--- 31name: sgpr_spill_s64_undef_low32 32tracksRegLiveness: true 33machineFunctionInfo: 34 isEntryFunction: true 35 hasSpilledSGPRs: true 36 scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' 37 stackPtrOffsetReg: '$sgpr32' 38 39stack: 40 - { id: 0, type: spill-slot, size: 8, alignment: 4, stack-id: sgpr-spill } 41 42body: | 43 bb.0: 44 liveins: $sgpr5 45 46 ; CHECK-LABEL: name: sgpr_spill_s64_undef_low32 47 ; CHECK: liveins: $sgpr5, $vgpr0 48 ; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr4, 0, undef $vgpr0, implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr5 49 ; CHECK: $vgpr0 = V_WRITELANE_B32 $sgpr5, 1, $vgpr0, implicit $sgpr4_sgpr5 50 SI_SPILL_S64_SAVE renamable $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 8 into %stack.0, align 4, addrspace 5) 51 52... 53