1; RUN: llc -march=amdgcn -mcpu=tahiti -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX6 %s 2; RUN: llc -march=amdgcn -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8-10 %s 3; RUN: llc -march=amdgcn -mcpu=gfx1010 -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX8-10 %s 4 5; GCN-LABEL: name: s_shl_i32 6; GCN: S_LSHL_B32 7define amdgpu_kernel void @s_shl_i32(i32 addrspace(1)* %out, i32 %lhs, i32 %rhs) { 8 %result = shl i32 %lhs, %rhs 9 store i32 %result, i32 addrspace(1)* %out 10 ret void 11} 12 13; GCN-LABEL: name: v_shl_i32 14; GFX6: V_LSHL_B32_e32 15; GFX8-10: V_LSHLREV_B32_e32 16define amdgpu_kernel void @v_shl_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { 17 %tid = call i32 @llvm.amdgcn.workitem.id.x() 18 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid 19 %a = load i32, i32 addrspace(1)* %in 20 %b = load i32, i32 addrspace(1)* %b_ptr 21 %result = shl i32 %a, %b 22 store i32 %result, i32 addrspace(1)* %out 23 ret void 24} 25 26; GCN-LABEL: name: s_lshr_i32 27; GCN: S_LSHR_B32 28define amdgpu_kernel void @s_lshr_i32(i32 addrspace(1)* %out, i32 %lhs, i32 %rhs) { 29 %result = lshr i32 %lhs, %rhs 30 store i32 %result, i32 addrspace(1)* %out 31 ret void 32} 33 34; GCN-LABEL: name: v_lshr_i32 35; GFX6: V_LSHR_B32_e32 36; GFX8-10: V_LSHRREV_B32_e64 37define amdgpu_kernel void @v_lshr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { 38 %tid = call i32 @llvm.amdgcn.workitem.id.x() 39 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid 40 %a = load i32, i32 addrspace(1)* %in 41 %b = load i32, i32 addrspace(1)* %b_ptr 42 %result = lshr i32 %a, %b 43 store i32 %result, i32 addrspace(1)* %out 44 ret void 45} 46 47; GCN-LABEL: name: s_ashr_i32 48; GCN: S_ASHR_I32 49define amdgpu_kernel void @s_ashr_i32(i32 addrspace(1)* %out, i32 %lhs, i32 %rhs) #0 { 50 %result = ashr i32 %lhs, %rhs 51 store i32 %result, i32 addrspace(1)* %out 52 ret void 53} 54 55; GCN-LABEL: name: v_ashr_i32 56; GFX6: V_ASHR_I32_e32 57; GFX8-10: V_ASHRREV_I32_e64 58define amdgpu_kernel void @v_ashr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { 59 %tid = call i32 @llvm.amdgcn.workitem.id.x() 60 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid 61 %a = load i32, i32 addrspace(1)* %in 62 %b = load i32, i32 addrspace(1)* %b_ptr 63 %result = ashr i32 %a, %b 64 store i32 %result, i32 addrspace(1)* %out 65 ret void 66} 67 68; GCN-LABEL: name: s_shl_i64 69; GCN: S_LSHL_B64 70define amdgpu_kernel void @s_shl_i64(i64 addrspace(1)* %out, i64 %lhs, i64 %rhs) { 71 %result = shl i64 %lhs, %rhs 72 store i64 %result, i64 addrspace(1)* %out 73 ret void 74} 75 76; GCN-LABEL: name: v_shl_i64 77; GFX6: V_LSHL_B64 78; GFX8: V_LSHLREV_B64 79define amdgpu_kernel void @v_shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 80 %tid = call i32 @llvm.amdgcn.workitem.id.x() 81 %idx = zext i32 %tid to i64 82 %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 %idx 83 %a = load i64, i64 addrspace(1)* %in 84 %b = load i64, i64 addrspace(1)* %b_ptr 85 %result = shl i64 %a, %b 86 store i64 %result, i64 addrspace(1)* %out 87 ret void 88} 89 90; GCN-LABEL: name: s_lshr_i64 91; GCN: S_LSHR_B64 92define amdgpu_kernel void @s_lshr_i64(i64 addrspace(1)* %out, i64 %lhs, i64 %rhs) { 93 %result = lshr i64 %lhs, %rhs 94 store i64 %result, i64 addrspace(1)* %out 95 ret void 96} 97 98; GCN-LABEL: name: v_lshr_i64 99; GFX6: V_LSHR_B64 100; GFX8: V_LSHRREV_B64 101define amdgpu_kernel void @v_lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 102 %tid = call i32 @llvm.amdgcn.workitem.id.x() 103 %idx = zext i32 %tid to i64 104 %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 %idx 105 %a = load i64, i64 addrspace(1)* %in 106 %b = load i64, i64 addrspace(1)* %b_ptr 107 %result = lshr i64 %a, %b 108 store i64 %result, i64 addrspace(1)* %out 109 ret void 110} 111 112; GCN-LABEL: name: s_ashr_i64 113; GCN: S_ASHR_I64 114define amdgpu_kernel void @s_ashr_i64(i64 addrspace(1)* %out, i64 %lhs, i64 %rhs) { 115 %result = ashr i64 %lhs, %rhs 116 store i64 %result, i64 addrspace(1)* %out 117 ret void 118} 119 120; GCN-LABEL: name: v_ashr_i64 121; GFX6: V_ASHR_I64 122; GFX8: V_ASHRREV_I64 123define amdgpu_kernel void @v_ashr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { 124 %tid = call i32 @llvm.amdgcn.workitem.id.x() 125 %idx = zext i32 %tid to i64 126 %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 %idx 127 %a = load i64, i64 addrspace(1)* %in 128 %b = load i64, i64 addrspace(1)* %b_ptr 129 %result = ashr i64 %a, %b 130 store i64 %result, i64 addrspace(1)* %out 131 ret void 132} 133 134declare i32 @llvm.amdgcn.workitem.id.x() 135