1; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 2; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 3 4; GCN-LABEL: {{^}}sitofp_i16_to_f16 5; GCN: buffer_load_{{sshort|ushort}} v[[A_I16:[0-9]+]] 6 7; SI: v_cvt_f32_i32_e32 v[[A_F32:[0-9]+]], v[[A_I16]] 8; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_F32]] 9 10; VI: v_cvt_f16_i16_e32 v[[R_F16:[0-9]+]], v[[A_I16]] 11 12; GCN: buffer_store_short v[[R_F16]] 13; GCN: s_endpgm 14define amdgpu_kernel void @sitofp_i16_to_f16( 15 half addrspace(1)* %r, 16 i16 addrspace(1)* %a) { 17entry: 18 %a.val = load i16, i16 addrspace(1)* %a 19 %r.val = sitofp i16 %a.val to half 20 store half %r.val, half addrspace(1)* %r 21 ret void 22} 23 24; GCN-LABEL: {{^}}sitofp_i32_to_f16 25; GCN: buffer_load_dword v[[A_I32:[0-9]+]] 26; GCN: v_cvt_f32_i32_e32 v[[A_I16:[0-9]+]], v[[A_I32]] 27; GCN: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[A_I16]] 28; GCN: buffer_store_short v[[R_F16]] 29; GCN: s_endpgm 30define amdgpu_kernel void @sitofp_i32_to_f16( 31 half addrspace(1)* %r, 32 i32 addrspace(1)* %a) { 33entry: 34 %a.val = load i32, i32 addrspace(1)* %a 35 %r.val = sitofp i32 %a.val to half 36 store half %r.val, half addrspace(1)* %r 37 ret void 38} 39 40; f16 = sitofp i64 is in sint_to_fp.i64.ll 41 42; GCN-LABEL: {{^}}sitofp_v2i16_to_v2f16 43; GCN: buffer_load_dword 44 45; SI: v_cvt_f32_i32_e32 46; SI: v_cvt_f32_i32_e32 47; SI: v_cvt_f16_f32_e32 48; SI: v_cvt_f16_f32_e32 49; SI-DAG: v_lshlrev_b32_e32 50; SI: v_or_b32_e32 51 52; VI-DAG: v_cvt_f16_i16_sdwa v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 53; VI-DAG: v_cvt_f16_i16_e32 54; VI: v_or_b32_e32 55 56; GCN: buffer_store_dword 57; GCN: s_endpgm 58 59define amdgpu_kernel void @sitofp_v2i16_to_v2f16( 60 <2 x half> addrspace(1)* %r, 61 <2 x i16> addrspace(1)* %a) { 62entry: 63 %a.val = load <2 x i16>, <2 x i16> addrspace(1)* %a 64 %r.val = sitofp <2 x i16> %a.val to <2 x half> 65 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 66 ret void 67} 68 69; GCN-LABEL: {{^}}sitofp_v2i32_to_v2f16 70; GCN: buffer_load_dwordx2 71 72; SI: v_cvt_f32_i32_e32 73; SI: v_cvt_f32_i32_e32 74; SI: v_cvt_f16_f32_e32 75; SI: v_cvt_f16_f32_e32 76; SI-DAG: v_lshlrev_b32_e32 77; SI: v_or_b32_e32 78 79; VI-DAG: v_cvt_f32_i32_e32 80; VI-DAG: v_cvt_f32_i32_e32 81; VI-DAG: v_cvt_f16_f32_e32 82; VI-DAG: v_cvt_f16_f32_sdwa 83; VI: v_or_b32_e32 84 85; GCN: buffer_store_dword 86; GCN: s_endpgm 87define amdgpu_kernel void @sitofp_v2i32_to_v2f16( 88 <2 x half> addrspace(1)* %r, 89 <2 x i32> addrspace(1)* %a) { 90entry: 91 %a.val = load <2 x i32>, <2 x i32> addrspace(1)* %a 92 %r.val = sitofp <2 x i32> %a.val to <2 x half> 93 store <2 x half> %r.val, <2 x half> addrspace(1)* %r 94 ret void 95} 96 97; GCN-LABEL: {{^}}s_sint_to_fp_i1_to_f16: 98; GCN-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 1.0, {{v[0-9]+}} 99; GCN-DAG: v_cmp_le_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, {{v[0-9]+}} 100; GCN: s_xor_b64 [[R_CMP:s\[[0-9]+:[0-9]+\]]], [[CMP1]], [[CMP0]] 101; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1.0, [[R_CMP]] 102; GCN-NEXT: v_cvt_f16_f32_e32 [[R_F16:v[0-9]+]], [[RESULT]] 103; GCN: buffer_store_short 104; GCN: s_endpgm 105define amdgpu_kernel void @s_sint_to_fp_i1_to_f16(half addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) { 106 %a = load float, float addrspace(1) * %in0 107 %b = load float, float addrspace(1) * %in1 108 %acmp = fcmp oge float %a, 0.000000e+00 109 %bcmp = fcmp oge float %b, 1.000000e+00 110 %result = xor i1 %acmp, %bcmp 111 %fp = sitofp i1 %result to half 112 store half %fp, half addrspace(1)* %out 113 ret void 114} 115 116; v2f16 = sitofp v2i64 is in sint_to_fp.i64.ll 117