1; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GCN %s 2 3; GCN-LABEL: {{^}}smrd_imm_dlc: 4; GCN: s_buffer_load_dword s0, s[0:3], 0x0 dlc ; encoding: [0x00,0x40,0x20,0xf4,0x00,0x00,0x00,0xfa] 5define amdgpu_ps float @smrd_imm_dlc(<4 x i32> inreg %desc) #0 { 6main_body: 7 %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 0, i32 4) 8 ret float %r 9} 10 11; GCN-LABEL: {{^}}smrd_sgpr_dlc: 12; GCN: s_buffer_load_dword s0, s[0:3], s4 dlc ; encoding: [0x00,0x40,0x20,0xf4,0x00,0x00,0x00,0x08] 13define amdgpu_ps float @smrd_sgpr_dlc(<4 x i32> inreg %desc, i32 inreg %offset) #0 { 14main_body: 15 %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %offset, i32 4) 16 ret float %r 17} 18 19; GCN-LABEL: {{^}}smrd_imm_glc_dlc: 20; GCN: s_buffer_load_dword s0, s[0:3], 0x0 glc dlc ; encoding: [0x00,0x40,0x21,0xf4,0x00,0x00,0x00,0xfa] 21define amdgpu_ps float @smrd_imm_glc_dlc(<4 x i32> inreg %desc) #0 { 22main_body: 23 %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 0, i32 5) 24 ret float %r 25} 26 27; GCN-LABEL: {{^}}smrd_sgpr_glc_dlc: 28; GCN: s_buffer_load_dword s0, s[0:3], s4 glc dlc ; encoding: [0x00,0x40,0x21,0xf4,0x00,0x00,0x00,0x08] 29define amdgpu_ps float @smrd_sgpr_glc_dlc(<4 x i32> inreg %desc, i32 inreg %offset) #0 { 30main_body: 31 %r = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %desc, i32 %offset, i32 5) 32 ret float %r 33} 34 35declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) 36 37!0 = !{} 38