1; RUN: llc -march=amdgcn -mcpu=verde -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 < %s | FileCheck -check-prefixes=CHECK,GFX6 %s 2; RUN: llc -regalloc=basic -march=amdgcn -mcpu=tonga -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 < %s | FileCheck -check-prefixes=CHECK,GFX7 %s 3; RUN: llc -march=amdgcn -mcpu=gfx900 -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 -amdgpu-enable-flat-scratch < %s | FileCheck -check-prefixes=CHECK,GFX9-FLATSCR,FLATSCR %s 4; RUN: llc -march=amdgcn -mcpu=gfx1030 -enable-misched=0 -post-RA-scheduler=0 -amdgpu-spill-sgpr-to-vgpr=0 -amdgpu-enable-flat-scratch < %s | FileCheck -check-prefixes=CHECK,GFX10-FLATSCR,FLATSCR %s 5; 6; There is something about Tonga that causes this test to spend a lot of time 7; in the default register allocator. 8 9 10; When the offset of VGPR spills into scratch space gets too large, an additional SGPR 11; is used to calculate the scratch load/store address. Make sure that this 12; mechanism works even when many spills happen. 13 14; Just test that it compiles successfully. 15; CHECK-LABEL: test 16 17; GFX9-FLATSCR: s_mov_b32 [[SOFF1:s[0-9]+]], 4{{$}} 18; GFX9-FLATSCR-DAG: scratch_store_dword off, v{{[0-9]+}}, [[SOFF1]] ; 4-byte Folded Spill 19; GFX9-FLATSCR-DAG: scratch_store_dword off, v{{[0-9]+}}, [[SOFF1]] offset:{{[0-9]+}} ; 4-byte Folded Spill 20; GFX9-FLATSCR: s_movk_i32 [[SOFF2:s[0-9]+]], 0x{{[0-9a-f]+}}{{$}} 21; GFX9-FLATSCR-DAG: scratch_load_dword v{{[0-9]+}}, off, [[SOFF2]] ; 4-byte Folded Reload 22; GFX9-FLATSCR-DAG: scratch_load_dword v{{[0-9]+}}, off, [[SOFF2]] offset:{{[0-9]+}} ; 4-byte Folded Reload 23 24; GFX10-FLATSCR: scratch_store_dword off, v{{[0-9]+}}, off offset:{{[0-9]+}} ; 4-byte Folded Spill 25; GFX10-FLATSCR: scratch_load_dword v{{[0-9]+}}, off, off offset:{{[0-9]+}} ; 4-byte Folded Reload 26define amdgpu_kernel void @test(<1280 x i32> addrspace(1)* %out, <1280 x i32> addrspace(1)* %in) { 27entry: 28 %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) 29 %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) 30 31 %aptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %in, i32 %tid 32 %a = load <1280 x i32>, <1280 x i32> addrspace(1)* %aptr 33 34; mark most VGPR registers as used to increase register pressure 35 call void asm sideeffect "", "~{v4},~{v8},~{v12},~{v16},~{v20},~{v24},~{v28},~{v32}" () 36 call void asm sideeffect "", "~{v36},~{v40},~{v44},~{v48},~{v52},~{v56},~{v60},~{v64}" () 37 call void asm sideeffect "", "~{v68},~{v72},~{v76},~{v80},~{v84},~{v88},~{v92},~{v96}" () 38 call void asm sideeffect "", "~{v100},~{v104},~{v108},~{v112},~{v116},~{v120},~{v124},~{v128}" () 39 call void asm sideeffect "", "~{v132},~{v136},~{v140},~{v144},~{v148},~{v152},~{v156},~{v160}" () 40 call void asm sideeffect "", "~{v164},~{v168},~{v172},~{v176},~{v180},~{v184},~{v188},~{v192}" () 41 call void asm sideeffect "", "~{v196},~{v200},~{v204},~{v208},~{v212},~{v216},~{v220},~{v224}" () 42 43 %outptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %out, i32 %tid 44 store <1280 x i32> %a, <1280 x i32> addrspace(1)* %outptr 45 46 ret void 47} 48 49; CHECK-LABEL: test_limited_sgpr 50; GFX6: s_add_u32 s32, s32, 0x[[OFFSET:[0-9a-f]+]] 51; GFX6-NEXT: buffer_load_dword v{{[0-9]+}}, off, s[{{[0-9:]+}}], s32 52; GFX6-NEXT: s_sub_u32 s32, s32, 0x[[OFFSET:[0-9a-f]+]] 53; GFX6: NumSgprs: 48 54; GFX6: ScratchSize: 8608 55 56; FLATSCR: s_movk_i32 [[SOFF1:s[0-9]+]], 0x 57; GFX9-FLATSCR-NEXT: s_waitcnt vmcnt(0) 58; FLATSCR-NEXT: scratch_store_dword off, v{{[0-9]+}}, [[SOFF1]] ; 4-byte Folded Spill 59; FLATSCR: s_movk_i32 [[SOFF2:s[0-9]+]], 0x 60; FLATSCR: scratch_load_dword v{{[0-9]+}}, off, [[SOFF2]] ; 4-byte Folded Reload 61define amdgpu_kernel void @test_limited_sgpr(<64 x i32> addrspace(1)* %out, <64 x i32> addrspace(1)* %in) #0 { 62entry: 63 %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) 64 %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) 65 66; allocate enough scratch to go beyond 2^12 addressing 67 %scratch = alloca <1280 x i32>, align 8, addrspace(5) 68 69; load VGPR data 70 %aptr = getelementptr <64 x i32>, <64 x i32> addrspace(1)* %in, i32 %tid 71 %a = load <64 x i32>, <64 x i32> addrspace(1)* %aptr 72 73; make sure scratch is used 74 %x = extractelement <64 x i32> %a, i32 0 75 %sptr0 = getelementptr <1280 x i32>, <1280 x i32> addrspace(5)* %scratch, i32 %x, i32 0 76 store i32 1, i32 addrspace(5)* %sptr0 77 78; fill up SGPRs 79 %sgpr0 = call <8 x i32> asm sideeffect "; def $0", "=s" () 80 %sgpr1 = call <8 x i32> asm sideeffect "; def $0", "=s" () 81 %sgpr2 = call <8 x i32> asm sideeffect "; def $0", "=s" () 82 %sgpr3 = call <8 x i32> asm sideeffect "; def $0", "=s" () 83 %sgpr4 = call <4 x i32> asm sideeffect "; def $0", "=s" () 84 %sgpr5 = call <2 x i32> asm sideeffect "; def $0", "=s" () 85 %sgpr6 = call <2 x i32> asm sideeffect "; def $0", "=s" () 86 %sgpr7 = call i32 asm sideeffect "; def $0", "=s" () 87 88 %cmp = icmp eq i32 %x, 0 89 br i1 %cmp, label %bb0, label %ret 90 91bb0: 92; create SGPR pressure 93 call void asm sideeffect "; use $0,$1,$2,$3,$4,$5,$6", "s,s,s,s,s,s,s,s"(<8 x i32> %sgpr0, <8 x i32> %sgpr1, <8 x i32> %sgpr2, <8 x i32> %sgpr3, <4 x i32> %sgpr4, <2 x i32> %sgpr5, <2 x i32> %sgpr6, i32 %sgpr7) 94 95; mark most VGPR registers as used to increase register pressure 96 call void asm sideeffect "", "~{v4},~{v8},~{v12},~{v16},~{v20},~{v24},~{v28},~{v32}" () 97 call void asm sideeffect "", "~{v36},~{v40},~{v44},~{v48},~{v52},~{v56},~{v60},~{v64}" () 98 call void asm sideeffect "", "~{v68},~{v72},~{v76},~{v80},~{v84},~{v88},~{v92},~{v96}" () 99 call void asm sideeffect "", "~{v100},~{v104},~{v108},~{v112},~{v116},~{v120},~{v124},~{v128}" () 100 call void asm sideeffect "", "~{v132},~{v136},~{v140},~{v144},~{v148},~{v152},~{v156},~{v160}" () 101 call void asm sideeffect "", "~{v164},~{v168},~{v172},~{v176},~{v180},~{v184},~{v188},~{v192}" () 102 call void asm sideeffect "", "~{v196},~{v200},~{v204},~{v208},~{v212},~{v216},~{v220},~{v224}" () 103 br label %ret 104 105ret: 106 %outptr = getelementptr <64 x i32>, <64 x i32> addrspace(1)* %out, i32 %tid 107 store <64 x i32> %a, <64 x i32> addrspace(1)* %outptr 108 109 ret void 110} 111 112declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 113declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1 114 115attributes #0 = { "amdgpu-waves-per-eu"="10,10" } 116attributes #1 = { nounwind readnone } 117