1; RUN: llc -O0 -march=amdgcn -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-O0 %s 2; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-O3 %s 3 4; GFX9-LABEL: {{^}}no_cfg: 5define amdgpu_cs void @no_cfg(<4 x i32> inreg %tmp14) { 6 %tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0) 7 %tmp101 = bitcast <2 x float> %tmp100 to <2 x i32> 8 %tmp102 = extractelement <2 x i32> %tmp101, i32 0 9 %tmp103 = extractelement <2 x i32> %tmp101, i32 1 10 %tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0) 11 %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0) 12 13; GFX9: s_or_saveexec_b64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, -1 14 15; GFX9-DAG: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf 16; GFX9-DAG: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] 17; GFX9-DAG: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]] 18 %tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false) 19 %tmp121 = add i32 %tmp105, %tmp120 20 %tmp122 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp121) 21 22; GFX9-DAG: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf 23; GFX9-DAG: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] 24; GFX9-DAG: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]] 25 %tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false) 26 %tmp136 = add i32 %tmp107, %tmp135 27 %tmp137 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp136) 28 29; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]] 30; GFX9-O0: v_cmp_eq_u32_e64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v[[FIRST]], v[[SECOND]] 31 %tmp138 = icmp eq i32 %tmp122, %tmp137 32 %tmp139 = sext i1 %tmp138 to i32 33 %tmp140 = shl nsw i32 %tmp139, 1 34 %tmp141 = and i32 %tmp140, 2 35 %tmp145 = bitcast i32 %tmp141 to float 36 call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0) 37 ret void 38} 39 40; GFX9-LABEL: {{^}}cfg: 41define amdgpu_cs void @cfg(<4 x i32> inreg %tmp14, i32 %arg) { 42entry: 43 %tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0) 44 %tmp101 = bitcast <2 x float> %tmp100 to <2 x i32> 45 %tmp102 = extractelement <2 x i32> %tmp101, i32 0 46 %tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0) 47 48; GFX9: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf 49; GFX9: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] 50; GFX9: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]] 51; GFX9-O0: buffer_store_dword v[[FIRST]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[FIRST_IMM_OFFSET:[0-9]+]] 52 %tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false) 53 %tmp121 = add i32 %tmp105, %tmp120 54 %tmp122 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp121) 55 56 %cond = icmp eq i32 %arg, 0 57 br i1 %cond, label %if, label %merge 58if: 59 %tmp103 = extractelement <2 x i32> %tmp101, i32 1 60 %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0) 61 62; GFX9: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf 63; GFX9: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] 64; GFX9: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]] 65; GFX9-O0: buffer_store_dword v[[SECOND]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[SECOND_IMM_OFFSET:[0-9]+]] 66 %tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false) 67 %tmp136 = add i32 %tmp107, %tmp135 68 %tmp137 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp136) 69 br label %merge 70 71merge: 72 %merge_value = phi i32 [ 0, %entry ], [%tmp137, %if ] 73; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]] 74; GFX9-O0: buffer_load_dword v[[FIRST:[0-9]+]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[FIRST_IMM_OFFSET]] 75; GFX9-O0: buffer_load_dword v[[SECOND:[0-9]+]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[SECOND_IMM_OFFSET]] 76; GFX9-O0: v_cmp_eq_u32_e64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v[[FIRST]], v[[SECOND]] 77 %tmp138 = icmp eq i32 %tmp122, %merge_value 78 %tmp139 = sext i1 %tmp138 to i32 79 %tmp140 = shl nsw i32 %tmp139, 1 80 %tmp141 = and i32 %tmp140, 2 81 %tmp145 = bitcast i32 %tmp141 to float 82 call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0) 83 ret void 84} 85 86; GFX9-LABEL: {{^}}called: 87define hidden i32 @called(i32 %a) noinline { 88; GFX9: v_add_u32_e32 v1, v0, v0 89 %add = add i32 %a, %a 90; GFX9: v_mul_lo_u32 v0, v1, v0 91 %mul = mul i32 %add, %a 92; GFX9: v_sub_u32_e32 v0, v0, v1 93 %sub = sub i32 %mul, %add 94 ret i32 %sub 95} 96 97; GFX9-LABEL: {{^}}call: 98define amdgpu_kernel void @call(<4 x i32> inreg %tmp14, i32 inreg %arg) { 99; GFX9-DAG: s_load_dword [[ARG:s[0-9]+]] 100; GFX9-O0-DAG: s_mov_b32 s0, 0{{$}} 101; GFX9-O0-DAG: v_mov_b32_e32 v0, [[ARG]] 102; GFX9-O0-DAG: v_mov_b32_e32 v2, v0 103 104; GFX9-O3: v_mov_b32_e32 v2, [[ARG]] 105 106; GFX9-NEXT: s_not_b64 exec, exec 107; GFX9-O0-NEXT: v_mov_b32_e32 v2, s0 108; GFX9-O3-NEXT: v_mov_b32_e32 v2, 0 109; GFX9-NEXT: s_not_b64 exec, exec 110 %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %arg, i32 0) 111; GFX9: v_mov_b32_e32 v0, v2 112; GFX9: s_swappc_b64 113 %tmp134 = call i32 @called(i32 %tmp107) 114; GFX9: v_mov_b32_e32 v1, v0 115; GFX9: v_add_u32_e32 v1, v1, v2 116 %tmp136 = add i32 %tmp134, %tmp107 117 %tmp137 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp136) 118; GFX9: buffer_store_dword v0 119 call void @llvm.amdgcn.raw.buffer.store.i32(i32 %tmp137, <4 x i32> %tmp14, i32 4, i32 0, i32 0) 120 ret void 121} 122 123; GFX9-LABEL: {{^}}called_i64: 124define i64 @called_i64(i64 %a) noinline { 125 %add = add i64 %a, %a 126 %mul = mul i64 %add, %a 127 %sub = sub i64 %mul, %add 128 ret i64 %sub 129} 130 131; GFX9-LABEL: {{^}}call_i64: 132define amdgpu_kernel void @call_i64(<4 x i32> inreg %tmp14, i64 inreg %arg) { 133; GFX9: s_load_dwordx2 s{{\[}}[[ARG_LO:[0-9]+]]:[[ARG_HI:[0-9]+]]{{\]}} 134 135; GFX9-O0: s_mov_b64 s{{\[}}[[ZERO_LO:[0-9]+]]:[[ZERO_HI:[0-9]+]]{{\]}}, 0{{$}} 136; GFX9-O0: v_mov_b32_e32 v0, s[[ARG_LO]] 137; GFX9-O0: v_mov_b32_e32 v1, s[[ARG_HI]] 138; GFX9-O0-DAG: v_mov_b32_e32 v10, v1 139; GFX9-O0-DAG: v_mov_b32_e32 v9, v0 140 141; GFX9-O3-DAG: v_mov_b32_e32 v7, s[[ARG_HI]] 142; GFX9-O3-DAG: v_mov_b32_e32 v6, s[[ARG_LO]] 143 144; GFX9: s_not_b64 exec, exec 145; GFX9-O0-NEXT: v_mov_b32_e32 v9, s[[ZERO_LO]] 146; GFX9-O0-NEXT: v_mov_b32_e32 v10, s[[ZERO_HI]] 147; GFX9-O3-NEXT: v_mov_b32_e32 v6, 0 148; GFX9-O3-NEXT: v_mov_b32_e32 v7, 0 149; GFX9-NEXT: s_not_b64 exec, exec 150 %tmp107 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %arg, i64 0) 151; GFX9: s_swappc_b64 152 %tmp134 = call i64 @called_i64(i64 %tmp107) 153 %tmp136 = add i64 %tmp134, %tmp107 154 %tmp137 = tail call i64 @llvm.amdgcn.wwm.i64(i64 %tmp136) 155 %tmp138 = bitcast i64 %tmp137 to <2 x i32> 156; GFX9: buffer_store_dwordx2 157 call void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32> %tmp138, <4 x i32> %tmp14, i32 4, i32 0, i32 0) 158 ret void 159} 160 161; GFX9-LABEL: {{^}}_amdgpu_cs_main: 162define amdgpu_cs void @_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %index) { 163 %tmp17 = shl i32 %index, 5 164; GFX9: buffer_load_dwordx4 165 %tmp18 = tail call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %desc, i32 %tmp17, i32 0) 166 %.i0.upto1.bc = bitcast <4 x i32> %tmp18 to <2 x i64> 167 %tmp19 = or i32 %tmp17, 16 168; GFX9: buffer_load_dwordx2 169 %tmp20 = tail call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %desc, i32 %tmp19, i32 0) 170 %.i0.upto1.extract = extractelement <2 x i64> %.i0.upto1.bc, i32 0 171 %tmp22 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i0.upto1.extract, i64 9223372036854775807) 172 %tmp97 = tail call i64 @llvm.amdgcn.wwm.i64(i64 %tmp22) 173 %.i1.upto1.extract = extractelement <2 x i64> %.i0.upto1.bc, i32 1 174 %tmp99 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i1.upto1.extract, i64 9223372036854775807) 175 %tmp174 = tail call i64 @llvm.amdgcn.wwm.i64(i64 %tmp99) 176 %.i25 = bitcast <2 x i32> %tmp20 to i64 177 %tmp176 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i25, i64 9223372036854775807) 178 %tmp251 = tail call i64 @llvm.amdgcn.wwm.i64(i64 %tmp176) 179 %.cast = bitcast i64 %tmp97 to <2 x float> 180 %.cast6 = bitcast i64 %tmp174 to <2 x float> 181 %.cast7 = bitcast i64 %tmp251 to <2 x float> 182 %tmp254 = shufflevector <2 x float> %.cast, <2 x float> %.cast6, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 183; GFX9: buffer_store_dwordx4 184 tail call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %tmp254, <4 x i32> %desc, i32 %tmp17, i32 0, i32 0) 185 ; GFX9: buffer_store_dwordx2 186 tail call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %.cast7, <4 x i32> %desc, i32 %tmp19, i32 0, i32 0) 187 ret void 188} 189 190declare i32 @llvm.amdgcn.wwm.i32(i32) 191declare i64 @llvm.amdgcn.wwm.i64(i64) 192declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) 193declare i64 @llvm.amdgcn.set.inactive.i64(i64, i64) 194declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) 195declare <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32>, i32, i32, i32) 196declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32) 197declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32) 198declare void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32>, <4 x i32>, i32, i32, i32) 199declare void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i32) 200declare void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32) 201declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32) 202declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i32) 203