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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc %s -o - -enable-shrink-wrap=true | FileCheck %s --check-prefix=ENABLE
3; RUN: llc %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=DISABLE
4; We cannot merge this test with the main test for shrink-wrapping, because
5; the code path we want to exerce is not taken with ios lowering.
6target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n8:16:32-S64"
7target triple = "armv7--linux-gnueabi"
8
9@skip = internal unnamed_addr constant [2 x i8] c"\01\01", align 1
10
11; Check that we do not restore the before having used the saved CSRs.
12; This happened because of a bad use of the post-dominance property.
13; The exit block of the loop happens to also lead to defs/uses of CSRs.
14; It also post-dominates the loop body and we use to generate invalid
15; restore sequence. I.e., we restored too early.
16
17define fastcc i8* @wrongUseOfPostDominate(i8* readonly %s, i32 %off, i8* readnone %lim) {
18; ENABLE-LABEL: wrongUseOfPostDominate:
19; ENABLE:       @ %bb.0: @ %entry
20; ENABLE-NEXT:    .save {r11, lr}
21; ENABLE-NEXT:    push {r11, lr}
22; ENABLE-NEXT:    cmn r1, #1
23; ENABLE-NEXT:    ble .LBB0_7
24; ENABLE-NEXT:  @ %bb.1: @ %while.cond.preheader
25; ENABLE-NEXT:    cmp r1, #0
26; ENABLE-NEXT:    beq .LBB0_6
27; ENABLE-NEXT:  @ %bb.2: @ %while.cond.preheader
28; ENABLE-NEXT:    cmp r0, r2
29; ENABLE-NEXT:    pophs {r11, pc}
30; ENABLE-NEXT:  .LBB0_3: @ %while.body.preheader
31; ENABLE-NEXT:    movw r12, :lower16:skip
32; ENABLE-NEXT:    sub r1, r1, #1
33; ENABLE-NEXT:    movt r12, :upper16:skip
34; ENABLE-NEXT:  .LBB0_4: @ %while.body
35; ENABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
36; ENABLE-NEXT:    ldrb r3, [r0]
37; ENABLE-NEXT:    ldrb r3, [r12, r3]
38; ENABLE-NEXT:    add r0, r0, r3
39; ENABLE-NEXT:    sub r3, r1, #1
40; ENABLE-NEXT:    cmp r3, r1
41; ENABLE-NEXT:    bhs .LBB0_6
42; ENABLE-NEXT:  @ %bb.5: @ %while.body
43; ENABLE-NEXT:    @ in Loop: Header=BB0_4 Depth=1
44; ENABLE-NEXT:    cmp r0, r2
45; ENABLE-NEXT:    mov r1, r3
46; ENABLE-NEXT:    blo .LBB0_4
47; ENABLE-NEXT:  .LBB0_6: @ %if.end29
48; ENABLE-NEXT:    pop {r11, pc}
49; ENABLE-NEXT:  .LBB0_7: @ %while.cond2.outer
50; ENABLE-NEXT:    @ =>This Loop Header: Depth=1
51; ENABLE-NEXT:    @ Child Loop BB0_8 Depth 2
52; ENABLE-NEXT:    @ Child Loop BB0_15 Depth 2
53; ENABLE-NEXT:    mov r3, r0
54; ENABLE-NEXT:  .LBB0_8: @ %while.cond2
55; ENABLE-NEXT:    @ Parent Loop BB0_7 Depth=1
56; ENABLE-NEXT:    @ => This Inner Loop Header: Depth=2
57; ENABLE-NEXT:    add r1, r1, #1
58; ENABLE-NEXT:    cmp r1, #1
59; ENABLE-NEXT:    beq .LBB0_18
60; ENABLE-NEXT:  @ %bb.9: @ %while.body4
61; ENABLE-NEXT:    @ in Loop: Header=BB0_8 Depth=2
62; ENABLE-NEXT:    cmp r3, r2
63; ENABLE-NEXT:    bls .LBB0_8
64; ENABLE-NEXT:  @ %bb.10: @ %if.then7
65; ENABLE-NEXT:    @ in Loop: Header=BB0_7 Depth=1
66; ENABLE-NEXT:    mov r0, r3
67; ENABLE-NEXT:    ldrb r12, [r0, #-1]!
68; ENABLE-NEXT:    sxtb lr, r12
69; ENABLE-NEXT:    cmn lr, #1
70; ENABLE-NEXT:    bgt .LBB0_7
71; ENABLE-NEXT:  @ %bb.11: @ %if.then7
72; ENABLE-NEXT:    @ in Loop: Header=BB0_7 Depth=1
73; ENABLE-NEXT:    cmp r0, r2
74; ENABLE-NEXT:    bls .LBB0_7
75; ENABLE-NEXT:  @ %bb.12: @ %land.rhs14.preheader
76; ENABLE-NEXT:    @ in Loop: Header=BB0_7 Depth=1
77; ENABLE-NEXT:    cmn lr, #1
78; ENABLE-NEXT:    bgt .LBB0_7
79; ENABLE-NEXT:  @ %bb.13: @ %land.rhs14.preheader
80; ENABLE-NEXT:    @ in Loop: Header=BB0_7 Depth=1
81; ENABLE-NEXT:    cmp r12, #191
82; ENABLE-NEXT:    bhi .LBB0_7
83; ENABLE-NEXT:  @ %bb.14: @ %while.body24.preheader
84; ENABLE-NEXT:    @ in Loop: Header=BB0_7 Depth=1
85; ENABLE-NEXT:    sub r3, r3, #2
86; ENABLE-NEXT:  .LBB0_15: @ %while.body24
87; ENABLE-NEXT:    @ Parent Loop BB0_7 Depth=1
88; ENABLE-NEXT:    @ => This Inner Loop Header: Depth=2
89; ENABLE-NEXT:    mov r0, r3
90; ENABLE-NEXT:    cmp r3, r2
91; ENABLE-NEXT:    bls .LBB0_7
92; ENABLE-NEXT:  @ %bb.16: @ %while.body24.land.rhs14_crit_edge
93; ENABLE-NEXT:    @ in Loop: Header=BB0_15 Depth=2
94; ENABLE-NEXT:    mov r3, r0
95; ENABLE-NEXT:    ldrsb lr, [r3], #-1
96; ENABLE-NEXT:    cmn lr, #1
97; ENABLE-NEXT:    uxtb r12, lr
98; ENABLE-NEXT:    bgt .LBB0_7
99; ENABLE-NEXT:  @ %bb.17: @ %while.body24.land.rhs14_crit_edge
100; ENABLE-NEXT:    @ in Loop: Header=BB0_15 Depth=2
101; ENABLE-NEXT:    cmp r12, #192
102; ENABLE-NEXT:    blo .LBB0_15
103; ENABLE-NEXT:    b .LBB0_7
104; ENABLE-NEXT:  .LBB0_18:
105; ENABLE-NEXT:    mov r0, r3
106; ENABLE-NEXT:    pop {r11, pc}
107;
108; DISABLE-LABEL: wrongUseOfPostDominate:
109; DISABLE:       @ %bb.0: @ %entry
110; DISABLE-NEXT:    .save {r11, lr}
111; DISABLE-NEXT:    push {r11, lr}
112; DISABLE-NEXT:    cmn r1, #1
113; DISABLE-NEXT:    ble .LBB0_7
114; DISABLE-NEXT:  @ %bb.1: @ %while.cond.preheader
115; DISABLE-NEXT:    cmp r1, #0
116; DISABLE-NEXT:    beq .LBB0_6
117; DISABLE-NEXT:  @ %bb.2: @ %while.cond.preheader
118; DISABLE-NEXT:    cmp r0, r2
119; DISABLE-NEXT:    pophs {r11, pc}
120; DISABLE-NEXT:  .LBB0_3: @ %while.body.preheader
121; DISABLE-NEXT:    movw r12, :lower16:skip
122; DISABLE-NEXT:    sub r1, r1, #1
123; DISABLE-NEXT:    movt r12, :upper16:skip
124; DISABLE-NEXT:  .LBB0_4: @ %while.body
125; DISABLE-NEXT:    @ =>This Inner Loop Header: Depth=1
126; DISABLE-NEXT:    ldrb r3, [r0]
127; DISABLE-NEXT:    ldrb r3, [r12, r3]
128; DISABLE-NEXT:    add r0, r0, r3
129; DISABLE-NEXT:    sub r3, r1, #1
130; DISABLE-NEXT:    cmp r3, r1
131; DISABLE-NEXT:    bhs .LBB0_6
132; DISABLE-NEXT:  @ %bb.5: @ %while.body
133; DISABLE-NEXT:    @ in Loop: Header=BB0_4 Depth=1
134; DISABLE-NEXT:    cmp r0, r2
135; DISABLE-NEXT:    mov r1, r3
136; DISABLE-NEXT:    blo .LBB0_4
137; DISABLE-NEXT:  .LBB0_6: @ %if.end29
138; DISABLE-NEXT:    pop {r11, pc}
139; DISABLE-NEXT:  .LBB0_7: @ %while.cond2.outer
140; DISABLE-NEXT:    @ =>This Loop Header: Depth=1
141; DISABLE-NEXT:    @ Child Loop BB0_8 Depth 2
142; DISABLE-NEXT:    @ Child Loop BB0_15 Depth 2
143; DISABLE-NEXT:    mov r3, r0
144; DISABLE-NEXT:  .LBB0_8: @ %while.cond2
145; DISABLE-NEXT:    @ Parent Loop BB0_7 Depth=1
146; DISABLE-NEXT:    @ => This Inner Loop Header: Depth=2
147; DISABLE-NEXT:    add r1, r1, #1
148; DISABLE-NEXT:    cmp r1, #1
149; DISABLE-NEXT:    beq .LBB0_18
150; DISABLE-NEXT:  @ %bb.9: @ %while.body4
151; DISABLE-NEXT:    @ in Loop: Header=BB0_8 Depth=2
152; DISABLE-NEXT:    cmp r3, r2
153; DISABLE-NEXT:    bls .LBB0_8
154; DISABLE-NEXT:  @ %bb.10: @ %if.then7
155; DISABLE-NEXT:    @ in Loop: Header=BB0_7 Depth=1
156; DISABLE-NEXT:    mov r0, r3
157; DISABLE-NEXT:    ldrb r12, [r0, #-1]!
158; DISABLE-NEXT:    sxtb lr, r12
159; DISABLE-NEXT:    cmn lr, #1
160; DISABLE-NEXT:    bgt .LBB0_7
161; DISABLE-NEXT:  @ %bb.11: @ %if.then7
162; DISABLE-NEXT:    @ in Loop: Header=BB0_7 Depth=1
163; DISABLE-NEXT:    cmp r0, r2
164; DISABLE-NEXT:    bls .LBB0_7
165; DISABLE-NEXT:  @ %bb.12: @ %land.rhs14.preheader
166; DISABLE-NEXT:    @ in Loop: Header=BB0_7 Depth=1
167; DISABLE-NEXT:    cmn lr, #1
168; DISABLE-NEXT:    bgt .LBB0_7
169; DISABLE-NEXT:  @ %bb.13: @ %land.rhs14.preheader
170; DISABLE-NEXT:    @ in Loop: Header=BB0_7 Depth=1
171; DISABLE-NEXT:    cmp r12, #191
172; DISABLE-NEXT:    bhi .LBB0_7
173; DISABLE-NEXT:  @ %bb.14: @ %while.body24.preheader
174; DISABLE-NEXT:    @ in Loop: Header=BB0_7 Depth=1
175; DISABLE-NEXT:    sub r3, r3, #2
176; DISABLE-NEXT:  .LBB0_15: @ %while.body24
177; DISABLE-NEXT:    @ Parent Loop BB0_7 Depth=1
178; DISABLE-NEXT:    @ => This Inner Loop Header: Depth=2
179; DISABLE-NEXT:    mov r0, r3
180; DISABLE-NEXT:    cmp r3, r2
181; DISABLE-NEXT:    bls .LBB0_7
182; DISABLE-NEXT:  @ %bb.16: @ %while.body24.land.rhs14_crit_edge
183; DISABLE-NEXT:    @ in Loop: Header=BB0_15 Depth=2
184; DISABLE-NEXT:    mov r3, r0
185; DISABLE-NEXT:    ldrsb lr, [r3], #-1
186; DISABLE-NEXT:    cmn lr, #1
187; DISABLE-NEXT:    uxtb r12, lr
188; DISABLE-NEXT:    bgt .LBB0_7
189; DISABLE-NEXT:  @ %bb.17: @ %while.body24.land.rhs14_crit_edge
190; DISABLE-NEXT:    @ in Loop: Header=BB0_15 Depth=2
191; DISABLE-NEXT:    cmp r12, #192
192; DISABLE-NEXT:    blo .LBB0_15
193; DISABLE-NEXT:    b .LBB0_7
194; DISABLE-NEXT:  .LBB0_18:
195; DISABLE-NEXT:    mov r0, r3
196; DISABLE-NEXT:    pop {r11, pc}
197entry:
198  %cmp = icmp sgt i32 %off, -1
199  br i1 %cmp, label %while.cond.preheader, label %while.cond2.outer
200
201while.cond.preheader:                             ; preds = %entry
202  %tobool4 = icmp ne i32 %off, 0
203  %cmp15 = icmp ult i8* %s, %lim
204  %sel66 = and i1 %tobool4, %cmp15
205  br i1 %sel66, label %while.body, label %if.end29
206
207while.body:                                       ; preds = %while.body, %while.cond.preheader
208  %s.addr.08 = phi i8* [ %add.ptr, %while.body ], [ %s, %while.cond.preheader ]
209  %off.addr.07 = phi i32 [ %dec, %while.body ], [ %off, %while.cond.preheader ]
210  %dec = add nsw i32 %off.addr.07, -1
211  %tmp = load i8, i8* %s.addr.08, align 1, !tbaa !2
212  %idxprom = zext i8 %tmp to i32
213  %arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* @skip, i32 0, i32 %idxprom
214  %tmp1 = load i8, i8* %arrayidx, align 1, !tbaa !2
215  %conv = zext i8 %tmp1 to i32
216  %add.ptr = getelementptr inbounds i8, i8* %s.addr.08, i32 %conv
217  %tobool = icmp ne i32 %off.addr.07, 1
218  %cmp1 = icmp ult i8* %add.ptr, %lim
219  %sel6 = and i1 %tobool, %cmp1
220  br i1 %sel6, label %while.body, label %if.end29
221
222while.cond2.outer:                                ; preds = %while.body24.land.rhs14_crit_edge, %while.body24, %land.rhs14.preheader, %if.then7, %entry
223  %off.addr.1.ph = phi i32 [ %off, %entry ], [ %inc, %land.rhs14.preheader ], [ %inc, %if.then7 ], [ %inc, %while.body24.land.rhs14_crit_edge ], [ %inc, %while.body24 ]
224  %s.addr.1.ph = phi i8* [ %s, %entry ], [ %incdec.ptr, %land.rhs14.preheader ], [ %incdec.ptr, %if.then7 ], [ %lsr.iv, %while.body24.land.rhs14_crit_edge ], [ %lsr.iv, %while.body24 ]
225  br label %while.cond2
226
227while.cond2:                                      ; preds = %while.body4, %while.cond2.outer
228  %off.addr.1 = phi i32 [ %inc, %while.body4 ], [ %off.addr.1.ph, %while.cond2.outer ]
229  %inc = add nsw i32 %off.addr.1, 1
230  %tobool3 = icmp eq i32 %off.addr.1, 0
231  br i1 %tobool3, label %if.end29, label %while.body4
232
233while.body4:                                      ; preds = %while.cond2
234  %tmp2 = icmp ugt i8* %s.addr.1.ph, %lim
235  br i1 %tmp2, label %if.then7, label %while.cond2
236
237if.then7:                                         ; preds = %while.body4
238  %incdec.ptr = getelementptr inbounds i8, i8* %s.addr.1.ph, i32 -1
239  %tmp3 = load i8, i8* %incdec.ptr, align 1, !tbaa !2
240  %conv1525 = zext i8 %tmp3 to i32
241  %tobool9 = icmp slt i8 %tmp3, 0
242  %cmp129 = icmp ugt i8* %incdec.ptr, %lim
243  %or.cond13 = and i1 %tobool9, %cmp129
244  br i1 %or.cond13, label %land.rhs14.preheader, label %while.cond2.outer
245
246land.rhs14.preheader:                             ; preds = %if.then7
247  %cmp1624 = icmp slt i8 %tmp3, 0
248  %cmp2026 = icmp ult i32 %conv1525, 192
249  %or.cond27 = and i1 %cmp1624, %cmp2026
250  br i1 %or.cond27, label %while.body24.preheader, label %while.cond2.outer
251
252while.body24.preheader:                           ; preds = %land.rhs14.preheader
253  %scevgep = getelementptr i8, i8* %s.addr.1.ph, i32 -2
254  br label %while.body24
255
256while.body24:                                     ; preds = %while.body24.land.rhs14_crit_edge, %while.body24.preheader
257  %lsr.iv = phi i8* [ %scevgep, %while.body24.preheader ], [ %scevgep34, %while.body24.land.rhs14_crit_edge ]
258  %cmp12 = icmp ugt i8* %lsr.iv, %lim
259  br i1 %cmp12, label %while.body24.land.rhs14_crit_edge, label %while.cond2.outer
260
261while.body24.land.rhs14_crit_edge:                ; preds = %while.body24
262  %.pre = load i8, i8* %lsr.iv, align 1, !tbaa !2
263  %cmp16 = icmp slt i8 %.pre, 0
264  %conv15 = zext i8 %.pre to i32
265  %cmp20 = icmp ult i32 %conv15, 192
266  %or.cond = and i1 %cmp16, %cmp20
267  %scevgep34 = getelementptr i8, i8* %lsr.iv, i32 -1
268  br i1 %or.cond, label %while.body24, label %while.cond2.outer
269
270if.end29:                                         ; preds = %while.cond2, %while.body, %while.cond.preheader
271  %s.addr.3 = phi i8* [ %s, %while.cond.preheader ], [ %add.ptr, %while.body ], [ %s.addr.1.ph, %while.cond2 ]
272  ret i8* %s.addr.3
273}
274
275!llvm.module.flags = !{!0, !1}
276
277!0 = !{i32 1, !"wchar_size", i32 4}
278!1 = !{i32 1, !"min_enum_size", i32 4}
279!2 = !{!3, !3, i64 0}
280!3 = !{!"omnipotent char", !4, i64 0}
281!4 = !{!"Simple C/C++ TBAA"}
282