1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=armv8.6a-arm-none-eabi -mattr=+bf16,+neon,+fullfp16 < %s | FileCheck %s 3 4target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 5target triple = "armv8.6a-arm-none-eabi" 6 7define arm_aapcs_vfpcc bfloat @test_vgetq_lane_bf16_even(<8 x bfloat> %v) { 8; CHECK-LABEL: test_vgetq_lane_bf16_even: 9; CHECK: @ %bb.0: @ %entry 10; CHECK-NEXT: vmov.f32 s0, s3 11; CHECK-NEXT: bx lr 12entry: 13 %0 = extractelement <8 x bfloat> %v, i32 6 14 ret bfloat %0 15} 16 17define arm_aapcs_vfpcc bfloat @test_vgetq_lane_bf16_odd(<8 x bfloat> %v) { 18; CHECK-LABEL: test_vgetq_lane_bf16_odd: 19; CHECK: @ %bb.0: @ %entry 20; CHECK-NEXT: vmovx.f16 s0, s3 21; CHECK-NEXT: bx lr 22entry: 23 %0 = extractelement <8 x bfloat> %v, i32 7 24 ret bfloat %0 25} 26 27define arm_aapcs_vfpcc bfloat @test_vget_lane_bf16_even(<4 x bfloat> %v) { 28; CHECK-LABEL: test_vget_lane_bf16_even: 29; CHECK: @ %bb.0: @ %entry 30; CHECK-NEXT: vmov.f32 s0, s1 31; CHECK-NEXT: bx lr 32entry: 33 %0 = extractelement <4 x bfloat> %v, i32 2 34 ret bfloat %0 35} 36 37define arm_aapcs_vfpcc bfloat @test_vget_lane_bf16_odd(<4 x bfloat> %v) { 38; CHECK-LABEL: test_vget_lane_bf16_odd: 39; CHECK: @ %bb.0: @ %entry 40; CHECK-NEXT: vmovx.f16 s0, s0 41; CHECK-NEXT: bx lr 42entry: 43 %0 = extractelement <4 x bfloat> %v, i32 1 44 ret bfloat %0 45} 46