1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes CHECK,CHECK-THUMB 3; RUN: llc -mtriple=armv8.2a-arm-none-eabi -mattr=+fullfp16 %s -o - | FileCheck %s --check-prefixes CHECK,CHECK-ARM 4 5define i32 @test_ne(i32 %x, i32 %y, i32 %a, i32 %b) { 6; CHECK-LABEL: test_ne: 7; CHECK: @ %bb.0: @ %entry 8; CHECK-NEXT: vmov s0, r1 9; CHECK-NEXT: cmp r2, r3 10; CHECK-NEXT: vmov s2, r0 11; CHECK-NEXT: vcvt.f16.u32 s0, s0 12; CHECK-NEXT: vcvt.f16.u32 s2, s2 13; CHECK-NEXT: vseleq.f16 s0, s0, s2 14; CHECK-NEXT: vmov.f16 r0, s0 15; CHECK-NEXT: bx lr 16entry: 17 %x.half = uitofp i32 %x to half 18 %y.half = uitofp i32 %y to half 19 %cmp = icmp ne i32 %a, %b 20 %cond = select i1 %cmp, half %x.half, half %y.half 21 %0 = bitcast half %cond to i16 22 %1 = zext i16 %0 to i32 23 ret i32 %1 24} 25 26define i32 @test_eq(i32 %x, i32 %y, i32 %a, i32 %b) { 27; CHECK-LABEL: test_eq: 28; CHECK: @ %bb.0: @ %entry 29; CHECK-NEXT: vmov s0, r0 30; CHECK-NEXT: cmp r2, r3 31; CHECK-NEXT: vmov s2, r1 32; CHECK-NEXT: vcvt.f16.u32 s0, s0 33; CHECK-NEXT: vcvt.f16.u32 s2, s2 34; CHECK-NEXT: vseleq.f16 s0, s0, s2 35; CHECK-NEXT: vmov.f16 r0, s0 36; CHECK-NEXT: bx lr 37entry: 38 %x.half = uitofp i32 %x to half 39 %y.half = uitofp i32 %y to half 40 %cmp = icmp eq i32 %a, %b 41 %cond = select i1 %cmp, half %x.half, half %y.half 42 %0 = bitcast half %cond to i16 43 %1 = zext i16 %0 to i32 44 ret i32 %1 45} 46 47define i32 @test_gt(i32 %x, i32 %y, i32 %a, i32 %b) { 48; CHECK-LABEL: test_gt: 49; CHECK: @ %bb.0: @ %entry 50; CHECK-NEXT: vmov s0, r0 51; CHECK-NEXT: cmp r2, r3 52; CHECK-NEXT: vmov s2, r1 53; CHECK-NEXT: vcvt.f16.u32 s0, s0 54; CHECK-NEXT: vcvt.f16.u32 s2, s2 55; CHECK-NEXT: vselgt.f16 s0, s0, s2 56; CHECK-NEXT: vmov.f16 r0, s0 57; CHECK-NEXT: bx lr 58entry: 59 %x.half = uitofp i32 %x to half 60 %y.half = uitofp i32 %y to half 61 %cmp = icmp sgt i32 %a, %b 62 %cond = select i1 %cmp, half %x.half, half %y.half 63 %0 = bitcast half %cond to i16 64 %1 = zext i16 %0 to i32 65 ret i32 %1 66} 67 68define i32 @test_ge(i32 %x, i32 %y, i32 %a, i32 %b) { 69; CHECK-LABEL: test_ge: 70; CHECK: @ %bb.0: @ %entry 71; CHECK-NEXT: vmov s0, r0 72; CHECK-NEXT: cmp r2, r3 73; CHECK-NEXT: vmov s2, r1 74; CHECK-NEXT: vcvt.f16.u32 s0, s0 75; CHECK-NEXT: vcvt.f16.u32 s2, s2 76; CHECK-NEXT: vselge.f16 s0, s0, s2 77; CHECK-NEXT: vmov.f16 r0, s0 78; CHECK-NEXT: bx lr 79entry: 80 %x.half = uitofp i32 %x to half 81 %y.half = uitofp i32 %y to half 82 %cmp = icmp sge i32 %a, %b 83 %cond = select i1 %cmp, half %x.half, half %y.half 84 %0 = bitcast half %cond to i16 85 %1 = zext i16 %0 to i32 86 ret i32 %1 87} 88 89define i32 @test_lt(i32 %x, i32 %y, i32 %a, i32 %b) { 90; CHECK-LABEL: test_lt: 91; CHECK: @ %bb.0: @ %entry 92; CHECK-NEXT: vmov s0, r1 93; CHECK-NEXT: cmp r2, r3 94; CHECK-NEXT: vmov s2, r0 95; CHECK-NEXT: vcvt.f16.u32 s0, s0 96; CHECK-NEXT: vcvt.f16.u32 s2, s2 97; CHECK-NEXT: vselge.f16 s0, s0, s2 98; CHECK-NEXT: vmov.f16 r0, s0 99; CHECK-NEXT: bx lr 100entry: 101 %x.half = uitofp i32 %x to half 102 %y.half = uitofp i32 %y to half 103 %cmp = icmp slt i32 %a, %b 104 %cond = select i1 %cmp, half %x.half, half %y.half 105 %0 = bitcast half %cond to i16 106 %1 = zext i16 %0 to i32 107 ret i32 %1 108} 109 110define i32 @test_le(i32 %x, i32 %y, i32 %a, i32 %b) { 111; CHECK-LABEL: test_le: 112; CHECK: @ %bb.0: @ %entry 113; CHECK-NEXT: vmov s0, r1 114; CHECK-NEXT: cmp r2, r3 115; CHECK-NEXT: vmov s2, r0 116; CHECK-NEXT: vcvt.f16.u32 s0, s0 117; CHECK-NEXT: vcvt.f16.u32 s2, s2 118; CHECK-NEXT: vselgt.f16 s0, s0, s2 119; CHECK-NEXT: vmov.f16 r0, s0 120; CHECK-NEXT: bx lr 121entry: 122 %x.half = uitofp i32 %x to half 123 %y.half = uitofp i32 %y to half 124 %cmp = icmp sle i32 %a, %b 125 %cond = select i1 %cmp, half %x.half, half %y.half 126 %0 = bitcast half %cond to i16 127 %1 = zext i16 %0 to i32 128 ret i32 %1 129} 130 131define i32 @test_hi(i32 %x, i32 %y, i32 %a, i32 %b) { 132; CHECK-THUMB-LABEL: test_hi: 133; CHECK-THUMB: @ %bb.0: @ %entry 134; CHECK-THUMB-NEXT: vmov s0, r1 135; CHECK-THUMB-NEXT: cmp r2, r3 136; CHECK-THUMB-NEXT: vmov s2, r0 137; CHECK-THUMB-NEXT: vcvt.f16.u32 s0, s0 138; CHECK-THUMB-NEXT: vcvt.f16.u32 s2, s2 139; CHECK-THUMB-NEXT: it hi 140; CHECK-THUMB-NEXT: vmovhi.f32 s0, s2 141; CHECK-THUMB-NEXT: vmov.f16 r0, s0 142; CHECK-THUMB-NEXT: bx lr 143; 144; CHECK-ARM-LABEL: test_hi: 145; CHECK-ARM: @ %bb.0: @ %entry 146; CHECK-ARM-NEXT: vmov s0, r1 147; CHECK-ARM-NEXT: cmp r2, r3 148; CHECK-ARM-NEXT: vmov s2, r0 149; CHECK-ARM-NEXT: vcvt.f16.u32 s0, s0 150; CHECK-ARM-NEXT: vcvt.f16.u32 s2, s2 151; CHECK-ARM-NEXT: vmovhi.f32 s0, s2 152; CHECK-ARM-NEXT: vmov.f16 r0, s0 153; CHECK-ARM-NEXT: bx lr 154entry: 155 %x.half = uitofp i32 %x to half 156 %y.half = uitofp i32 %y to half 157 %cmp = icmp ugt i32 %a, %b 158 %cond = select i1 %cmp, half %x.half, half %y.half 159 %0 = bitcast half %cond to i16 160 %1 = zext i16 %0 to i32 161 ret i32 %1 162} 163 164define i32 @test_hs(i32 %x, i32 %y, i32 %a, i32 %b) { 165; CHECK-THUMB-LABEL: test_hs: 166; CHECK-THUMB: @ %bb.0: @ %entry 167; CHECK-THUMB-NEXT: vmov s0, r1 168; CHECK-THUMB-NEXT: cmp r2, r3 169; CHECK-THUMB-NEXT: vmov s2, r0 170; CHECK-THUMB-NEXT: vcvt.f16.u32 s0, s0 171; CHECK-THUMB-NEXT: vcvt.f16.u32 s2, s2 172; CHECK-THUMB-NEXT: it hs 173; CHECK-THUMB-NEXT: vmovhs.f32 s0, s2 174; CHECK-THUMB-NEXT: vmov.f16 r0, s0 175; CHECK-THUMB-NEXT: bx lr 176; 177; CHECK-ARM-LABEL: test_hs: 178; CHECK-ARM: @ %bb.0: @ %entry 179; CHECK-ARM-NEXT: vmov s0, r1 180; CHECK-ARM-NEXT: cmp r2, r3 181; CHECK-ARM-NEXT: vmov s2, r0 182; CHECK-ARM-NEXT: vcvt.f16.u32 s0, s0 183; CHECK-ARM-NEXT: vcvt.f16.u32 s2, s2 184; CHECK-ARM-NEXT: vmovhs.f32 s0, s2 185; CHECK-ARM-NEXT: vmov.f16 r0, s0 186; CHECK-ARM-NEXT: bx lr 187entry: 188 %x.half = uitofp i32 %x to half 189 %y.half = uitofp i32 %y to half 190 %cmp = icmp uge i32 %a, %b 191 %cond = select i1 %cmp, half %x.half, half %y.half 192 %0 = bitcast half %cond to i16 193 %1 = zext i16 %0 to i32 194 ret i32 %1 195} 196 197define i32 @test_lo(i32 %x, i32 %y, i32 %a, i32 %b) { 198; CHECK-THUMB-LABEL: test_lo: 199; CHECK-THUMB: @ %bb.0: @ %entry 200; CHECK-THUMB-NEXT: vmov s0, r1 201; CHECK-THUMB-NEXT: cmp r2, r3 202; CHECK-THUMB-NEXT: vmov s2, r0 203; CHECK-THUMB-NEXT: vcvt.f16.u32 s0, s0 204; CHECK-THUMB-NEXT: vcvt.f16.u32 s2, s2 205; CHECK-THUMB-NEXT: it lo 206; CHECK-THUMB-NEXT: vmovlo.f32 s0, s2 207; CHECK-THUMB-NEXT: vmov.f16 r0, s0 208; CHECK-THUMB-NEXT: bx lr 209; 210; CHECK-ARM-LABEL: test_lo: 211; CHECK-ARM: @ %bb.0: @ %entry 212; CHECK-ARM-NEXT: vmov s0, r1 213; CHECK-ARM-NEXT: cmp r2, r3 214; CHECK-ARM-NEXT: vmov s2, r0 215; CHECK-ARM-NEXT: vcvt.f16.u32 s0, s0 216; CHECK-ARM-NEXT: vcvt.f16.u32 s2, s2 217; CHECK-ARM-NEXT: vmovlo.f32 s0, s2 218; CHECK-ARM-NEXT: vmov.f16 r0, s0 219; CHECK-ARM-NEXT: bx lr 220entry: 221 %x.half = uitofp i32 %x to half 222 %y.half = uitofp i32 %y to half 223 %cmp = icmp ult i32 %a, %b 224 %cond = select i1 %cmp, half %x.half, half %y.half 225 %0 = bitcast half %cond to i16 226 %1 = zext i16 %0 to i32 227 ret i32 %1 228} 229 230define i32 @test_ls(i32 %x, i32 %y, i32 %a, i32 %b) { 231; CHECK-THUMB-LABEL: test_ls: 232; CHECK-THUMB: @ %bb.0: @ %entry 233; CHECK-THUMB-NEXT: vmov s0, r1 234; CHECK-THUMB-NEXT: cmp r2, r3 235; CHECK-THUMB-NEXT: vmov s2, r0 236; CHECK-THUMB-NEXT: vcvt.f16.u32 s0, s0 237; CHECK-THUMB-NEXT: vcvt.f16.u32 s2, s2 238; CHECK-THUMB-NEXT: it ls 239; CHECK-THUMB-NEXT: vmovls.f32 s0, s2 240; CHECK-THUMB-NEXT: vmov.f16 r0, s0 241; CHECK-THUMB-NEXT: bx lr 242; 243; CHECK-ARM-LABEL: test_ls: 244; CHECK-ARM: @ %bb.0: @ %entry 245; CHECK-ARM-NEXT: vmov s0, r1 246; CHECK-ARM-NEXT: cmp r2, r3 247; CHECK-ARM-NEXT: vmov s2, r0 248; CHECK-ARM-NEXT: vcvt.f16.u32 s0, s0 249; CHECK-ARM-NEXT: vcvt.f16.u32 s2, s2 250; CHECK-ARM-NEXT: vmovls.f32 s0, s2 251; CHECK-ARM-NEXT: vmov.f16 r0, s0 252; CHECK-ARM-NEXT: bx lr 253entry: 254 %x.half = uitofp i32 %x to half 255 %y.half = uitofp i32 %y to half 256 %cmp = icmp ule i32 %a, %b 257 %cond = select i1 %cmp, half %x.half, half %y.half 258 %0 = bitcast half %cond to i16 259 %1 = zext i16 %0 to i32 260 ret i32 %1 261} 262 263