1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s 3 4--- | 5 ; ModuleID = '<stdin>' 6 source_filename = "<stdin>" 7 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 8 target triple = "thumb-none--eabi" 9 10 define i32 @f(i32 %a, i32 %b) { 11 entry: 12 %mul = mul nsw i32 %b, %a 13 %cmp = icmp eq i32 %mul, 0 14 %conv = zext i1 %cmp to i32 15 ret i32 %conv 16 } 17 18... 19--- 20name: f 21alignment: 2 22exposesReturnsTwice: false 23legalized: false 24regBankSelected: false 25selected: false 26tracksRegLiveness: true 27registers: 28 - { id: 0, class: tgpr } 29 - { id: 1, class: tgpr } 30 - { id: 2, class: tgpr } 31 - { id: 3, class: tgpr } 32 - { id: 4, class: tgpr } 33 - { id: 5, class: tgpr } 34liveins: 35 - { reg: '$r0', virtual-reg: '%0' } 36 - { reg: '$r1', virtual-reg: '%1' } 37frameInfo: 38 isFrameAddressTaken: false 39 isReturnAddressTaken: false 40 hasStackMap: false 41 hasPatchPoint: false 42 stackSize: 0 43 offsetAdjustment: 0 44 maxAlignment: 0 45 adjustsStack: false 46 hasCalls: false 47 maxCallFrameSize: 0 48 hasOpaqueSPAdjustment: false 49 hasVAStart: false 50 hasMustTailInVarArgFunc: false 51 52body: | 53 ; CHECK-LABEL: name: f 54 ; CHECK: bb.0.entry: 55 ; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000) 56 ; CHECK: liveins: $r0, $r1 57 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r1 58 ; CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r0 59 ; CHECK: %3:tgpr, $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg 60 ; CHECK: %4:tgpr, $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg 61 ; CHECK: %2:tgpr, $cpsr = tMUL [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg 62 ; CHECK: tBcc %bb.2, 0 /* CC::eq */, $cpsr 63 ; CHECK: bb.1.entry: 64 ; CHECK: successors: %bb.2(0x80000000) 65 ; CHECK: bb.2.entry: 66 ; CHECK: [[PHI:%[0-9]+]]:tgpr = PHI %4, %bb.1, %3, %bb.0 67 ; CHECK: $r0 = COPY [[PHI]] 68 ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 69 bb.0.entry: 70 liveins: $r0, $r1 71 72 %1 = COPY $r1 73 %0 = COPY $r0 74 %2, $cpsr = tMUL %1, %0, 14, $noreg 75 %3, $cpsr = tMOVi8 1, 14, $noreg 76 %4, $cpsr = tMOVi8 0, 14, $noreg 77 tCMPi8 killed %2, 0, 14, $noreg, implicit-def $cpsr 78 tBcc %bb.2.entry, 0, $cpsr 79 80 bb.1.entry: 81 82 bb.2.entry: 83 %5 = PHI %4, %bb.1.entry, %3, %bb.0.entry 84 $r0 = COPY %5 85 tBX_RET 14, $noreg, implicit $r0 86 87... 88