1; REQUIRES: asserts 2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s 3; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=+use-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=POST-MISCHED 4 5; Check the latency for ALU shifted operand variants. 6; 7; CHECK: ********** MI Scheduling ********** 8; CHECK: foo:%bb.0 entry 9 10; ALU, basic - 1 cyc I0/I1 11; CHECK: EORrr 12; CHECK: rdefs left 13; CHECK-NEXT: Latency : 1 14 15; ALU, shift by immed - 2 cyc M 16; CHECK: ADDrsi 17; CHECK: rdefs left 18; CHECK-NEXT: Latency : 2 19 20; ALU, shift by register, unconditional - 2 cyc M 21; CHECK: RSBrsr 22; CHECK: rdefs left 23; CHECK-NEXT: Latency : 2 24 25; ALU, shift by register, conditional - 2 cyc I0/I1 26; CHECK: ANDrsr 27; CHECK: rdefs left 28; CHECK-NEXT: Latency : 2 29 30; Checking scheduling units 31 32; CHECK: ** ScheduleDAGMILive::schedule picking next node 33; Skipping COPY 34; CHECK: ** ScheduleDAGMILive::schedule picking next node 35; CHECK: Scheduling 36; CHECK-SAME: ANDrsr 37; CHECK: Ready 38; CHECK-NEXT: A57UnitI 39 40; CHECK: ** ScheduleDAGMILive::schedule picking next node 41; CHECK: Scheduling 42; CHECK-SAME: CMPri 43; CHECK: Ready 44; CHECK-NEXT: A57UnitI 45 46; CHECK: ** ScheduleDAGMILive::schedule picking next node 47; CHECK: Scheduling 48; CHECK-SAME: RSBrsr 49; CHECK: Ready 50; CHECK-NEXT: A57UnitM 51 52; CHECK: ** ScheduleDAGMILive::schedule picking next node 53; CHECK: Scheduling 54; CHECK-SAME: ADDrsi 55; CHECK: Ready 56; CHECK-NEXT: A57UnitM 57 58; CHECK: ** ScheduleDAGMILive::schedule picking next node 59; CHECK: Scheduling 60; CHECK-SAME: EORrr 61; CHECK: Ready 62; CHECK-NEXT: A57UnitI 63 64; Check that post RA MI scheduler is invoked with +use-misched 65; POST-MISCHED: Before post-MI-sched 66 67target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 68target triple = "armv8r-arm-none-eabi" 69 70; Function Attrs: norecurse nounwind readnone 71define hidden i32 @foo(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #0 { 72entry: 73 %xor = xor i32 %a, %b 74 %xor_shl = shl i32 %xor, 2 75 %add = add i32 %xor_shl, %d 76 %add_ashr = ashr i32 %add, %a 77 %sub = sub i32 %add_ashr, %a 78 %sub_lshr_pred = lshr i32 %sub, %c 79 %pred = icmp sgt i32 %a, 4 80 %and = and i32 %sub_lshr_pred, %b 81 %rv = select i1 %pred, i32 %and, i32 %d 82 ret i32 %rv 83} 84 85