1; REQUIRES: asserts 2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=A57_SCHED 3; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC 4 5; Check the latency for instructions for both generic and cortex-a57. 6; SDIV should be scheduled at the block's begin (20 cyc of independent M unit). 7; 8; CHECK: ********** MI Scheduling ********** 9; CHECK: foo:%bb.0 entry 10 11; GENERIC: LDRi12 12; GENERIC: Latency : 1 13; GENERIC: EORrr 14; GENERIC: Latency : 1 15; GENERIC: ADDrr 16; GENERIC: Latency : 1 17; GENERIC: SDIV 18; GENERIC: Latency : 0 19; GENERIC: SUBrr 20; GENERIC: Latency : 1 21 22; A57_SCHED: SDIV 23; A57_SCHED: Latency : 20 24; A57_SCHED: EORrr 25; A57_SCHED: Latency : 1 26; A57_SCHED: LDRi12 27; A57_SCHED: Latency : 4 28; A57_SCHED: ADDrr 29; A57_SCHED: Latency : 1 30; A57_SCHED: SUBrr 31; A57_SCHED: Latency : 1 32 33; CHECK: ** Final schedule for %bb.0 *** 34; GENERIC: LDRi12 35; GENERIC: SDIV 36; A57_SCHED: SDIV 37; A57_SCHED: LDRi12 38; CHECK: ********** INTERVALS ********** 39 40target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 41target triple = "armv8r-arm-none-eabi" 42 43; Function Attrs: norecurse nounwind readnone 44define hidden i32 @foo(i32 %a, i32 %b, i32 %c, i32* %d) local_unnamed_addr #0 { 45entry: 46 %xor = xor i32 %c, %b 47 %ld = load i32, i32* %d 48 %add = add nsw i32 %xor, %ld 49 %div = sdiv i32 %a, %b 50 %sub = sub i32 %div, %add 51 ret i32 %sub 52} 53 54