1; REQUIRES: asserts 2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s 3 4; CHECK: ********** MI Scheduling ********** 5; We need second, post-ra scheduling to have LDM instruction combined from single-loads 6; CHECK: ********** MI Scheduling ********** 7; CHECK: LDMIA 8; CHECK: rdefs left 9; CHECK-NEXT: Latency : 3 10; CHECK: Successors: 11; CHECK: Data 12; CHECK-SAME: Latency=3 13; CHECK-NEXT: Data 14; CHECK-SAME: Latency=0 15 16define i32 @foo(i32* %a) nounwind optsize { 17entry: 18 %b = getelementptr i32, i32* %a, i32 1 19 %c = getelementptr i32, i32* %a, i32 2 20 %0 = load i32, i32* %a, align 4 21 %1 = load i32, i32* %b, align 4 22 %2 = load i32, i32* %c, align 4 23 24 %mul1 = mul i32 %0, %1 25 %mul2 = mul i32 %mul1, %2 26 ret i32 %mul2 27} 28 29