1; REQUIRES: asserts 2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s 3; 4 5@a = global double 0.0, align 4 6@b = global double 0.0, align 4 7@c = global double 0.0, align 4 8 9; CHECK: ********** MI Scheduling ********** 10; We need second, post-ra scheduling to have VLDM instruction combined from single-loads 11; CHECK: ********** MI Scheduling ********** 12; CHECK: VLDMDIA_UPD 13; CHECK: rdefs left 14; CHECK-NEXT: Latency : 6 15; CHECK: Successors: 16; CHECK: Data 17; CHECK-SAME: Latency=1 18; CHECK-NEXT: Data 19; CHECK-SAME: Latency=1 20; CHECK-NEXT: Data 21; CHECK-SAME: Latency=5 22; CHECK-NEXT: Data 23; CHECK-SAME: Latency=0 24; CHECK-NEXT: Data 25; CHECK-SAME: Latency=0 26define i32 @bar(i32* %iptr) minsize optsize { 27 %1 = load double, double* @a, align 8 28 %2 = load double, double* @b, align 8 29 %3 = load double, double* @c, align 8 30 31 %ptr_after = getelementptr double, double* @a, i32 3 32 33 %ptr_new_ival = ptrtoint double* %ptr_after to i32 34 %ptr_new = inttoptr i32 %ptr_new_ival to i32* 35 36 store i32 %ptr_new_ival, i32* %iptr, align 8 37 38 %v1 = fptoui double %1 to i32 39 40 %mul1 = mul i32 %ptr_new_ival, %v1 41 42 %v2 = fptoui double %2 to i32 43 %v3 = fptoui double %3 to i32 44 45 %mul2 = mul i32 %mul1, %v2 46 %mul3 = mul i32 %mul2, %v3 47 48 ret i32 %mul3 49} 50 51