1; REQUIRES: asserts 2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s 3 4; CHECK: ********** MI Scheduling ********** 5; We need second, post-ra scheduling to have VLDM instruction combined from single-loads 6; CHECK: ********** MI Scheduling ********** 7; CHECK: VLDMDIA 8; CHECK: rdefs left 9; CHECK-NEXT: Latency : 6 10; CHECK: Successors: 11; CHECK: Data 12; CHECK-SAME: Latency=5 13; CHECK-NEXT: Data 14; CHECK-SAME: Latency=0 15; CHECK-NEXT: Data 16; CHECK-SAME: Latency=0 17 18define double @foo(double* %a) nounwind optsize { 19entry: 20 %b = getelementptr double, double* %a, i32 1 21 %c = getelementptr double, double* %a, i32 2 22 %0 = load double, double* %a, align 4 23 %1 = load double, double* %b, align 4 24 %2 = load double, double* %c, align 4 25 26 %mul1 = fmul double %0, %1 27 %mul2 = fmul double %mul1, %2 28 ret double %mul2 29} 30 31