1; REQUIRES: asserts 2; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s 3 4; CHECK: ********** MI Scheduling ********** 5; We need second, post-ra scheduling to have VSTM instruction combined from single-stores 6; CHECK: ********** MI Scheduling ********** 7; CHECK: schedule starting 8; CHECK: VSTMDIA_UPD 9; CHECK: rdefs left 10; CHECK-NEXT: Latency : 4 11; CHECK: Successors: 12; CHECK: Data 13; CHECK-SAME: Latency=1 14 15@a = global double 0.0, align 4 16@b = global double 0.0, align 4 17@c = global double 0.0, align 4 18 19define i32 @bar(double* %vptr, i32 %iv1, i32* %iptr) minsize { 20 21 %vp2 = getelementptr double, double* %vptr, i32 1 22 %vp3 = getelementptr double, double* %vptr, i32 2 23 24 %v1 = load double, double* %vptr, align 8 25 %v2 = load double, double* %vp2, align 8 26 %v3 = load double, double* %vp3, align 8 27 28 store double %v1, double* @a, align 8 29 store double %v2, double* @b, align 8 30 store double %v3, double* @c, align 8 31 32 %ptr_after = getelementptr double, double* @a, i32 3 33 34 %ptr_new_ival = ptrtoint double* %ptr_after to i32 35 %ptr_new = inttoptr i32 %ptr_new_ival to i32* 36 37 store i32 %ptr_new_ival, i32* %iptr, align 8 38 39 %mul1 = mul i32 %ptr_new_ival, %iv1 40 41 ret i32 %mul1 42} 43 44