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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=armv6 < %s | FileCheck %s --check-prefixes=ARM,ARM6
3; RUN: llc -mtriple=armv7 < %s | FileCheck %s --check-prefixes=ARM,ARM78
4; RUN: llc -mtriple=armv8a < %s | FileCheck %s --check-prefixes=ARM,ARM78
5; RUN: llc -mtriple=thumbv6 < %s | FileCheck %s --check-prefixes=THUMB6
6; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefixes=THUMB78,THUMB7
7; RUN: llc -mtriple=thumbv8-eabi < %s | FileCheck %s --check-prefixes=THUMB78,THUMB8
8
9; We are looking for the following pattern here:
10;   (X & (C << Y)) ==/!= 0
11; It may be optimal to hoist the constant:
12;   ((X l>> Y) & C) ==/!= 0
13
14;------------------------------------------------------------------------------;
15; A few scalar test
16;------------------------------------------------------------------------------;
17
18; i8 scalar
19
20define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {
21; ARM-LABEL: scalar_i8_signbit_eq:
22; ARM:       @ %bb.0:
23; ARM-NEXT:    uxtb r1, r1
24; ARM-NEXT:    uxtb r0, r0
25; ARM-NEXT:    lsr r0, r0, r1
26; ARM-NEXT:    mov r1, #1
27; ARM-NEXT:    eor r0, r1, r0, lsr #7
28; ARM-NEXT:    bx lr
29;
30; THUMB6-LABEL: scalar_i8_signbit_eq:
31; THUMB6:       @ %bb.0:
32; THUMB6-NEXT:    uxtb r1, r1
33; THUMB6-NEXT:    uxtb r0, r0
34; THUMB6-NEXT:    lsrs r0, r1
35; THUMB6-NEXT:    movs r1, #128
36; THUMB6-NEXT:    ands r1, r0
37; THUMB6-NEXT:    rsbs r0, r1, #0
38; THUMB6-NEXT:    adcs r0, r1
39; THUMB6-NEXT:    bx lr
40;
41; THUMB7-LABEL: scalar_i8_signbit_eq:
42; THUMB7:       @ %bb.0:
43; THUMB7-NEXT:    uxtb r1, r1
44; THUMB7-NEXT:    uxtb r0, r0
45; THUMB7-NEXT:    lsrs r0, r1
46; THUMB7-NEXT:    movs r1, #1
47; THUMB7-NEXT:    eor.w r0, r1, r0, lsr #7
48; THUMB7-NEXT:    bx lr
49;
50; THUMB8-LABEL: scalar_i8_signbit_eq:
51; THUMB8:       @ %bb.0:
52; THUMB8-NEXT:    uxtb r0, r0
53; THUMB8-NEXT:    uxtb r1, r1
54; THUMB8-NEXT:    lsrs r0, r1
55; THUMB8-NEXT:    movs r1, #1
56; THUMB8-NEXT:    eor.w r0, r1, r0, lsr #7
57; THUMB8-NEXT:    bx lr
58  %t0 = shl i8 128, %y
59  %t1 = and i8 %t0, %x
60  %res = icmp eq i8 %t1, 0
61  ret i1 %res
62}
63
64define i1 @scalar_i8_lowestbit_eq(i8 %x, i8 %y) nounwind {
65; ARM-LABEL: scalar_i8_lowestbit_eq:
66; ARM:       @ %bb.0:
67; ARM-NEXT:    uxtb r1, r1
68; ARM-NEXT:    uxtb r0, r0
69; ARM-NEXT:    mov r2, #1
70; ARM-NEXT:    bic r0, r2, r0, lsr r1
71; ARM-NEXT:    bx lr
72;
73; THUMB6-LABEL: scalar_i8_lowestbit_eq:
74; THUMB6:       @ %bb.0:
75; THUMB6-NEXT:    uxtb r1, r1
76; THUMB6-NEXT:    uxtb r0, r0
77; THUMB6-NEXT:    lsrs r0, r1
78; THUMB6-NEXT:    movs r1, #1
79; THUMB6-NEXT:    ands r1, r0
80; THUMB6-NEXT:    rsbs r0, r1, #0
81; THUMB6-NEXT:    adcs r0, r1
82; THUMB6-NEXT:    bx lr
83;
84; THUMB7-LABEL: scalar_i8_lowestbit_eq:
85; THUMB7:       @ %bb.0:
86; THUMB7-NEXT:    uxtb r1, r1
87; THUMB7-NEXT:    uxtb r0, r0
88; THUMB7-NEXT:    lsrs r0, r1
89; THUMB7-NEXT:    movs r1, #1
90; THUMB7-NEXT:    bic.w r0, r1, r0
91; THUMB7-NEXT:    bx lr
92;
93; THUMB8-LABEL: scalar_i8_lowestbit_eq:
94; THUMB8:       @ %bb.0:
95; THUMB8-NEXT:    uxtb r0, r0
96; THUMB8-NEXT:    uxtb r1, r1
97; THUMB8-NEXT:    lsrs r0, r1
98; THUMB8-NEXT:    movs r1, #1
99; THUMB8-NEXT:    bic.w r0, r1, r0
100; THUMB8-NEXT:    bx lr
101  %t0 = shl i8 1, %y
102  %t1 = and i8 %t0, %x
103  %res = icmp eq i8 %t1, 0
104  ret i1 %res
105}
106
107define i1 @scalar_i8_bitsinmiddle_eq(i8 %x, i8 %y) nounwind {
108; ARM-LABEL: scalar_i8_bitsinmiddle_eq:
109; ARM:       @ %bb.0:
110; ARM-NEXT:    uxtb r1, r1
111; ARM-NEXT:    uxtb r0, r0
112; ARM-NEXT:    mov r2, #24
113; ARM-NEXT:    and r0, r2, r0, lsr r1
114; ARM-NEXT:    clz r0, r0
115; ARM-NEXT:    lsr r0, r0, #5
116; ARM-NEXT:    bx lr
117;
118; THUMB6-LABEL: scalar_i8_bitsinmiddle_eq:
119; THUMB6:       @ %bb.0:
120; THUMB6-NEXT:    uxtb r1, r1
121; THUMB6-NEXT:    uxtb r0, r0
122; THUMB6-NEXT:    lsrs r0, r1
123; THUMB6-NEXT:    movs r1, #24
124; THUMB6-NEXT:    ands r1, r0
125; THUMB6-NEXT:    rsbs r0, r1, #0
126; THUMB6-NEXT:    adcs r0, r1
127; THUMB6-NEXT:    bx lr
128;
129; THUMB7-LABEL: scalar_i8_bitsinmiddle_eq:
130; THUMB7:       @ %bb.0:
131; THUMB7-NEXT:    uxtb r1, r1
132; THUMB7-NEXT:    uxtb r0, r0
133; THUMB7-NEXT:    lsrs r0, r1
134; THUMB7-NEXT:    and r0, r0, #24
135; THUMB7-NEXT:    clz r0, r0
136; THUMB7-NEXT:    lsrs r0, r0, #5
137; THUMB7-NEXT:    bx lr
138;
139; THUMB8-LABEL: scalar_i8_bitsinmiddle_eq:
140; THUMB8:       @ %bb.0:
141; THUMB8-NEXT:    uxtb r0, r0
142; THUMB8-NEXT:    uxtb r1, r1
143; THUMB8-NEXT:    lsrs r0, r1
144; THUMB8-NEXT:    and r0, r0, #24
145; THUMB8-NEXT:    clz r0, r0
146; THUMB8-NEXT:    lsrs r0, r0, #5
147; THUMB8-NEXT:    bx lr
148  %t0 = shl i8 24, %y
149  %t1 = and i8 %t0, %x
150  %res = icmp eq i8 %t1, 0
151  ret i1 %res
152}
153
154; i16 scalar
155
156define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {
157; ARM-LABEL: scalar_i16_signbit_eq:
158; ARM:       @ %bb.0:
159; ARM-NEXT:    uxth r1, r1
160; ARM-NEXT:    uxth r0, r0
161; ARM-NEXT:    lsr r0, r0, r1
162; ARM-NEXT:    mov r1, #1
163; ARM-NEXT:    eor r0, r1, r0, lsr #15
164; ARM-NEXT:    bx lr
165;
166; THUMB6-LABEL: scalar_i16_signbit_eq:
167; THUMB6:       @ %bb.0:
168; THUMB6-NEXT:    uxth r1, r1
169; THUMB6-NEXT:    uxth r0, r0
170; THUMB6-NEXT:    lsrs r0, r1
171; THUMB6-NEXT:    movs r1, #1
172; THUMB6-NEXT:    lsls r1, r1, #15
173; THUMB6-NEXT:    ands r1, r0
174; THUMB6-NEXT:    rsbs r0, r1, #0
175; THUMB6-NEXT:    adcs r0, r1
176; THUMB6-NEXT:    bx lr
177;
178; THUMB7-LABEL: scalar_i16_signbit_eq:
179; THUMB7:       @ %bb.0:
180; THUMB7-NEXT:    uxth r1, r1
181; THUMB7-NEXT:    uxth r0, r0
182; THUMB7-NEXT:    lsrs r0, r1
183; THUMB7-NEXT:    movs r1, #1
184; THUMB7-NEXT:    eor.w r0, r1, r0, lsr #15
185; THUMB7-NEXT:    bx lr
186;
187; THUMB8-LABEL: scalar_i16_signbit_eq:
188; THUMB8:       @ %bb.0:
189; THUMB8-NEXT:    uxth r0, r0
190; THUMB8-NEXT:    uxth r1, r1
191; THUMB8-NEXT:    lsrs r0, r1
192; THUMB8-NEXT:    movs r1, #1
193; THUMB8-NEXT:    eor.w r0, r1, r0, lsr #15
194; THUMB8-NEXT:    bx lr
195  %t0 = shl i16 32768, %y
196  %t1 = and i16 %t0, %x
197  %res = icmp eq i16 %t1, 0
198  ret i1 %res
199}
200
201define i1 @scalar_i16_lowestbit_eq(i16 %x, i16 %y) nounwind {
202; ARM-LABEL: scalar_i16_lowestbit_eq:
203; ARM:       @ %bb.0:
204; ARM-NEXT:    uxth r1, r1
205; ARM-NEXT:    uxth r0, r0
206; ARM-NEXT:    mov r2, #1
207; ARM-NEXT:    bic r0, r2, r0, lsr r1
208; ARM-NEXT:    bx lr
209;
210; THUMB6-LABEL: scalar_i16_lowestbit_eq:
211; THUMB6:       @ %bb.0:
212; THUMB6-NEXT:    uxth r1, r1
213; THUMB6-NEXT:    uxth r0, r0
214; THUMB6-NEXT:    lsrs r0, r1
215; THUMB6-NEXT:    movs r1, #1
216; THUMB6-NEXT:    ands r1, r0
217; THUMB6-NEXT:    rsbs r0, r1, #0
218; THUMB6-NEXT:    adcs r0, r1
219; THUMB6-NEXT:    bx lr
220;
221; THUMB7-LABEL: scalar_i16_lowestbit_eq:
222; THUMB7:       @ %bb.0:
223; THUMB7-NEXT:    uxth r1, r1
224; THUMB7-NEXT:    uxth r0, r0
225; THUMB7-NEXT:    lsrs r0, r1
226; THUMB7-NEXT:    movs r1, #1
227; THUMB7-NEXT:    bic.w r0, r1, r0
228; THUMB7-NEXT:    bx lr
229;
230; THUMB8-LABEL: scalar_i16_lowestbit_eq:
231; THUMB8:       @ %bb.0:
232; THUMB8-NEXT:    uxth r0, r0
233; THUMB8-NEXT:    uxth r1, r1
234; THUMB8-NEXT:    lsrs r0, r1
235; THUMB8-NEXT:    movs r1, #1
236; THUMB8-NEXT:    bic.w r0, r1, r0
237; THUMB8-NEXT:    bx lr
238  %t0 = shl i16 1, %y
239  %t1 = and i16 %t0, %x
240  %res = icmp eq i16 %t1, 0
241  ret i1 %res
242}
243
244define i1 @scalar_i16_bitsinmiddle_eq(i16 %x, i16 %y) nounwind {
245; ARM-LABEL: scalar_i16_bitsinmiddle_eq:
246; ARM:       @ %bb.0:
247; ARM-NEXT:    uxth r1, r1
248; ARM-NEXT:    uxth r0, r0
249; ARM-NEXT:    mov r2, #4080
250; ARM-NEXT:    and r0, r2, r0, lsr r1
251; ARM-NEXT:    clz r0, r0
252; ARM-NEXT:    lsr r0, r0, #5
253; ARM-NEXT:    bx lr
254;
255; THUMB6-LABEL: scalar_i16_bitsinmiddle_eq:
256; THUMB6:       @ %bb.0:
257; THUMB6-NEXT:    uxth r1, r1
258; THUMB6-NEXT:    uxth r0, r0
259; THUMB6-NEXT:    lsrs r0, r1
260; THUMB6-NEXT:    movs r1, #255
261; THUMB6-NEXT:    lsls r1, r1, #4
262; THUMB6-NEXT:    ands r1, r0
263; THUMB6-NEXT:    rsbs r0, r1, #0
264; THUMB6-NEXT:    adcs r0, r1
265; THUMB6-NEXT:    bx lr
266;
267; THUMB7-LABEL: scalar_i16_bitsinmiddle_eq:
268; THUMB7:       @ %bb.0:
269; THUMB7-NEXT:    uxth r1, r1
270; THUMB7-NEXT:    uxth r0, r0
271; THUMB7-NEXT:    lsrs r0, r1
272; THUMB7-NEXT:    and r0, r0, #4080
273; THUMB7-NEXT:    clz r0, r0
274; THUMB7-NEXT:    lsrs r0, r0, #5
275; THUMB7-NEXT:    bx lr
276;
277; THUMB8-LABEL: scalar_i16_bitsinmiddle_eq:
278; THUMB8:       @ %bb.0:
279; THUMB8-NEXT:    uxth r0, r0
280; THUMB8-NEXT:    uxth r1, r1
281; THUMB8-NEXT:    lsrs r0, r1
282; THUMB8-NEXT:    and r0, r0, #4080
283; THUMB8-NEXT:    clz r0, r0
284; THUMB8-NEXT:    lsrs r0, r0, #5
285; THUMB8-NEXT:    bx lr
286  %t0 = shl i16 4080, %y
287  %t1 = and i16 %t0, %x
288  %res = icmp eq i16 %t1, 0
289  ret i1 %res
290}
291
292; i32 scalar
293
294define i1 @scalar_i32_signbit_eq(i32 %x, i32 %y) nounwind {
295; ARM-LABEL: scalar_i32_signbit_eq:
296; ARM:       @ %bb.0:
297; ARM-NEXT:    mvn r0, r0, lsr r1
298; ARM-NEXT:    lsr r0, r0, #31
299; ARM-NEXT:    bx lr
300;
301; THUMB6-LABEL: scalar_i32_signbit_eq:
302; THUMB6:       @ %bb.0:
303; THUMB6-NEXT:    lsrs r0, r1
304; THUMB6-NEXT:    movs r1, #1
305; THUMB6-NEXT:    lsls r1, r1, #31
306; THUMB6-NEXT:    ands r1, r0
307; THUMB6-NEXT:    rsbs r0, r1, #0
308; THUMB6-NEXT:    adcs r0, r1
309; THUMB6-NEXT:    bx lr
310;
311; THUMB78-LABEL: scalar_i32_signbit_eq:
312; THUMB78:       @ %bb.0:
313; THUMB78-NEXT:    lsrs r0, r1
314; THUMB78-NEXT:    mvns r0, r0
315; THUMB78-NEXT:    lsrs r0, r0, #31
316; THUMB78-NEXT:    bx lr
317  %t0 = shl i32 2147483648, %y
318  %t1 = and i32 %t0, %x
319  %res = icmp eq i32 %t1, 0
320  ret i1 %res
321}
322
323define i1 @scalar_i32_lowestbit_eq(i32 %x, i32 %y) nounwind {
324; ARM-LABEL: scalar_i32_lowestbit_eq:
325; ARM:       @ %bb.0:
326; ARM-NEXT:    mov r2, #1
327; ARM-NEXT:    bic r0, r2, r0, lsr r1
328; ARM-NEXT:    bx lr
329;
330; THUMB6-LABEL: scalar_i32_lowestbit_eq:
331; THUMB6:       @ %bb.0:
332; THUMB6-NEXT:    lsrs r0, r1
333; THUMB6-NEXT:    movs r1, #1
334; THUMB6-NEXT:    ands r1, r0
335; THUMB6-NEXT:    rsbs r0, r1, #0
336; THUMB6-NEXT:    adcs r0, r1
337; THUMB6-NEXT:    bx lr
338;
339; THUMB78-LABEL: scalar_i32_lowestbit_eq:
340; THUMB78:       @ %bb.0:
341; THUMB78-NEXT:    lsrs r0, r1
342; THUMB78-NEXT:    movs r1, #1
343; THUMB78-NEXT:    bic.w r0, r1, r0
344; THUMB78-NEXT:    bx lr
345  %t0 = shl i32 1, %y
346  %t1 = and i32 %t0, %x
347  %res = icmp eq i32 %t1, 0
348  ret i1 %res
349}
350
351define i1 @scalar_i32_bitsinmiddle_eq(i32 %x, i32 %y) nounwind {
352; ARM6-LABEL: scalar_i32_bitsinmiddle_eq:
353; ARM6:       @ %bb.0:
354; ARM6-NEXT:    mov r2, #65280
355; ARM6-NEXT:    orr r2, r2, #16711680
356; ARM6-NEXT:    and r0, r2, r0, lsr r1
357; ARM6-NEXT:    clz r0, r0
358; ARM6-NEXT:    lsr r0, r0, #5
359; ARM6-NEXT:    bx lr
360;
361; ARM78-LABEL: scalar_i32_bitsinmiddle_eq:
362; ARM78:       @ %bb.0:
363; ARM78-NEXT:    movw r2, #65280
364; ARM78-NEXT:    movt r2, #255
365; ARM78-NEXT:    and r0, r2, r0, lsr r1
366; ARM78-NEXT:    clz r0, r0
367; ARM78-NEXT:    lsr r0, r0, #5
368; ARM78-NEXT:    bx lr
369;
370; THUMB6-LABEL: scalar_i32_bitsinmiddle_eq:
371; THUMB6:       @ %bb.0:
372; THUMB6-NEXT:    lsrs r0, r1
373; THUMB6-NEXT:    ldr r1, .LCPI8_0
374; THUMB6-NEXT:    ands r1, r0
375; THUMB6-NEXT:    rsbs r0, r1, #0
376; THUMB6-NEXT:    adcs r0, r1
377; THUMB6-NEXT:    bx lr
378; THUMB6-NEXT:    .p2align 2
379; THUMB6-NEXT:  @ %bb.1:
380; THUMB6-NEXT:  .LCPI8_0:
381; THUMB6-NEXT:    .long 16776960 @ 0xffff00
382;
383; THUMB78-LABEL: scalar_i32_bitsinmiddle_eq:
384; THUMB78:       @ %bb.0:
385; THUMB78-NEXT:    lsrs r0, r1
386; THUMB78-NEXT:    movw r1, #65280
387; THUMB78-NEXT:    movt r1, #255
388; THUMB78-NEXT:    ands r0, r1
389; THUMB78-NEXT:    clz r0, r0
390; THUMB78-NEXT:    lsrs r0, r0, #5
391; THUMB78-NEXT:    bx lr
392  %t0 = shl i32 16776960, %y
393  %t1 = and i32 %t0, %x
394  %res = icmp eq i32 %t1, 0
395  ret i1 %res
396}
397
398; i64 scalar
399
400define i1 @scalar_i64_signbit_eq(i64 %x, i64 %y) nounwind {
401; ARM6-LABEL: scalar_i64_signbit_eq:
402; ARM6:       @ %bb.0:
403; ARM6-NEXT:    lsr r0, r1, r2
404; ARM6-NEXT:    subs r1, r2, #32
405; ARM6-NEXT:    movpl r0, #0
406; ARM6-NEXT:    mvn r0, r0
407; ARM6-NEXT:    lsr r0, r0, #31
408; ARM6-NEXT:    bx lr
409;
410; ARM78-LABEL: scalar_i64_signbit_eq:
411; ARM78:       @ %bb.0:
412; ARM78-NEXT:    lsr r0, r1, r2
413; ARM78-NEXT:    subs r1, r2, #32
414; ARM78-NEXT:    movwpl r0, #0
415; ARM78-NEXT:    mvn r0, r0
416; ARM78-NEXT:    lsr r0, r0, #31
417; ARM78-NEXT:    bx lr
418;
419; THUMB6-LABEL: scalar_i64_signbit_eq:
420; THUMB6:       @ %bb.0:
421; THUMB6-NEXT:    push {r7, lr}
422; THUMB6-NEXT:    bl __lshrdi3
423; THUMB6-NEXT:    movs r0, #1
424; THUMB6-NEXT:    lsls r2, r0, #31
425; THUMB6-NEXT:    ands r2, r1
426; THUMB6-NEXT:    rsbs r0, r2, #0
427; THUMB6-NEXT:    adcs r0, r2
428; THUMB6-NEXT:    pop {r7, pc}
429;
430; THUMB78-LABEL: scalar_i64_signbit_eq:
431; THUMB78:       @ %bb.0:
432; THUMB78-NEXT:    lsr.w r0, r1, r2
433; THUMB78-NEXT:    subs.w r1, r2, #32
434; THUMB78-NEXT:    it pl
435; THUMB78-NEXT:    movpl r0, #0
436; THUMB78-NEXT:    mvns r0, r0
437; THUMB78-NEXT:    lsrs r0, r0, #31
438; THUMB78-NEXT:    bx lr
439  %t0 = shl i64 9223372036854775808, %y
440  %t1 = and i64 %t0, %x
441  %res = icmp eq i64 %t1, 0
442  ret i1 %res
443}
444
445define i1 @scalar_i64_lowestbit_eq(i64 %x, i64 %y) nounwind {
446; ARM-LABEL: scalar_i64_lowestbit_eq:
447; ARM:       @ %bb.0:
448; ARM-NEXT:    rsb r3, r2, #32
449; ARM-NEXT:    lsr r0, r0, r2
450; ARM-NEXT:    subs r2, r2, #32
451; ARM-NEXT:    orr r0, r0, r1, lsl r3
452; ARM-NEXT:    lsrpl r0, r1, r2
453; ARM-NEXT:    mov r1, #1
454; ARM-NEXT:    bic r0, r1, r0
455; ARM-NEXT:    bx lr
456;
457; THUMB6-LABEL: scalar_i64_lowestbit_eq:
458; THUMB6:       @ %bb.0:
459; THUMB6-NEXT:    push {r7, lr}
460; THUMB6-NEXT:    bl __lshrdi3
461; THUMB6-NEXT:    movs r1, #1
462; THUMB6-NEXT:    ands r1, r0
463; THUMB6-NEXT:    rsbs r0, r1, #0
464; THUMB6-NEXT:    adcs r0, r1
465; THUMB6-NEXT:    pop {r7, pc}
466;
467; THUMB7-LABEL: scalar_i64_lowestbit_eq:
468; THUMB7:       @ %bb.0:
469; THUMB7-NEXT:    rsb.w r3, r2, #32
470; THUMB7-NEXT:    lsrs r0, r2
471; THUMB7-NEXT:    subs r2, #32
472; THUMB7-NEXT:    lsl.w r3, r1, r3
473; THUMB7-NEXT:    orr.w r0, r0, r3
474; THUMB7-NEXT:    it pl
475; THUMB7-NEXT:    lsrpl.w r0, r1, r2
476; THUMB7-NEXT:    movs r1, #1
477; THUMB7-NEXT:    bic.w r0, r1, r0
478; THUMB7-NEXT:    bx lr
479;
480; THUMB8-LABEL: scalar_i64_lowestbit_eq:
481; THUMB8:       @ %bb.0:
482; THUMB8-NEXT:    rsb.w r3, r2, #32
483; THUMB8-NEXT:    lsrs r0, r2
484; THUMB8-NEXT:    lsl.w r3, r1, r3
485; THUMB8-NEXT:    orrs r0, r3
486; THUMB8-NEXT:    subs r2, #32
487; THUMB8-NEXT:    lsr.w r1, r1, r2
488; THUMB8-NEXT:    it mi
489; THUMB8-NEXT:    movmi r1, r0
490; THUMB8-NEXT:    movs r0, #1
491; THUMB8-NEXT:    bics r0, r1
492; THUMB8-NEXT:    bx lr
493  %t0 = shl i64 1, %y
494  %t1 = and i64 %t0, %x
495  %res = icmp eq i64 %t1, 0
496  ret i1 %res
497}
498
499define i1 @scalar_i64_bitsinmiddle_eq(i64 %x, i64 %y) nounwind {
500; ARM6-LABEL: scalar_i64_bitsinmiddle_eq:
501; ARM6:       @ %bb.0:
502; ARM6-NEXT:    rsb r3, r2, #32
503; ARM6-NEXT:    lsr r0, r0, r2
504; ARM6-NEXT:    orr r0, r0, r1, lsl r3
505; ARM6-NEXT:    subs r3, r2, #32
506; ARM6-NEXT:    lsrpl r0, r1, r3
507; ARM6-NEXT:    lsr r1, r1, r2
508; ARM6-NEXT:    movpl r1, #0
509; ARM6-NEXT:    pkhbt r0, r1, r0
510; ARM6-NEXT:    clz r0, r0
511; ARM6-NEXT:    lsr r0, r0, #5
512; ARM6-NEXT:    bx lr
513;
514; ARM78-LABEL: scalar_i64_bitsinmiddle_eq:
515; ARM78:       @ %bb.0:
516; ARM78-NEXT:    rsb r3, r2, #32
517; ARM78-NEXT:    lsr r0, r0, r2
518; ARM78-NEXT:    orr r0, r0, r1, lsl r3
519; ARM78-NEXT:    subs r3, r2, #32
520; ARM78-NEXT:    lsrpl r0, r1, r3
521; ARM78-NEXT:    lsr r1, r1, r2
522; ARM78-NEXT:    movwpl r1, #0
523; ARM78-NEXT:    pkhbt r0, r1, r0
524; ARM78-NEXT:    clz r0, r0
525; ARM78-NEXT:    lsr r0, r0, #5
526; ARM78-NEXT:    bx lr
527;
528; THUMB6-LABEL: scalar_i64_bitsinmiddle_eq:
529; THUMB6:       @ %bb.0:
530; THUMB6-NEXT:    push {r7, lr}
531; THUMB6-NEXT:    bl __lshrdi3
532; THUMB6-NEXT:    ldr r2, .LCPI11_0
533; THUMB6-NEXT:    ands r2, r0
534; THUMB6-NEXT:    uxth r0, r1
535; THUMB6-NEXT:    adds r1, r2, r0
536; THUMB6-NEXT:    rsbs r0, r1, #0
537; THUMB6-NEXT:    adcs r0, r1
538; THUMB6-NEXT:    pop {r7, pc}
539; THUMB6-NEXT:    .p2align 2
540; THUMB6-NEXT:  @ %bb.1:
541; THUMB6-NEXT:  .LCPI11_0:
542; THUMB6-NEXT:    .long 4294901760 @ 0xffff0000
543;
544; THUMB7-LABEL: scalar_i64_bitsinmiddle_eq:
545; THUMB7:       @ %bb.0:
546; THUMB7-NEXT:    rsb.w r3, r2, #32
547; THUMB7-NEXT:    lsrs r0, r2
548; THUMB7-NEXT:    lsl.w r3, r1, r3
549; THUMB7-NEXT:    orrs r0, r3
550; THUMB7-NEXT:    subs.w r3, r2, #32
551; THUMB7-NEXT:    it pl
552; THUMB7-NEXT:    lsrpl.w r0, r1, r3
553; THUMB7-NEXT:    lsr.w r1, r1, r2
554; THUMB7-NEXT:    it pl
555; THUMB7-NEXT:    movpl r1, #0
556; THUMB7-NEXT:    pkhbt r0, r1, r0
557; THUMB7-NEXT:    clz r0, r0
558; THUMB7-NEXT:    lsrs r0, r0, #5
559; THUMB7-NEXT:    bx lr
560;
561; THUMB8-LABEL: scalar_i64_bitsinmiddle_eq:
562; THUMB8:       @ %bb.0:
563; THUMB8-NEXT:    rsb.w r3, r2, #32
564; THUMB8-NEXT:    lsrs r0, r2
565; THUMB8-NEXT:    lsl.w r3, r1, r3
566; THUMB8-NEXT:    orrs r0, r3
567; THUMB8-NEXT:    subs.w r3, r2, #32
568; THUMB8-NEXT:    lsr.w r3, r1, r3
569; THUMB8-NEXT:    it mi
570; THUMB8-NEXT:    movmi r3, r0
571; THUMB8-NEXT:    lsr.w r0, r1, r2
572; THUMB8-NEXT:    it pl
573; THUMB8-NEXT:    movpl r0, #0
574; THUMB8-NEXT:    pkhbt r0, r0, r3
575; THUMB8-NEXT:    clz r0, r0
576; THUMB8-NEXT:    lsrs r0, r0, #5
577; THUMB8-NEXT:    bx lr
578  %t0 = shl i64 281474976645120, %y
579  %t1 = and i64 %t0, %x
580  %res = icmp eq i64 %t1, 0
581  ret i1 %res
582}
583
584;------------------------------------------------------------------------------;
585; A few trivial vector tests
586;------------------------------------------------------------------------------;
587
588define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
589; ARM6-LABEL: vec_4xi32_splat_eq:
590; ARM6:       @ %bb.0:
591; ARM6-NEXT:    push {r11, lr}
592; ARM6-NEXT:    ldr r12, [sp, #8]
593; ARM6-NEXT:    mov lr, #1
594; ARM6-NEXT:    bic r0, lr, r0, lsr r12
595; ARM6-NEXT:    ldr r12, [sp, #12]
596; ARM6-NEXT:    bic r1, lr, r1, lsr r12
597; ARM6-NEXT:    ldr r12, [sp, #16]
598; ARM6-NEXT:    bic r2, lr, r2, lsr r12
599; ARM6-NEXT:    ldr r12, [sp, #20]
600; ARM6-NEXT:    bic r3, lr, r3, lsr r12
601; ARM6-NEXT:    pop {r11, pc}
602;
603; ARM78-LABEL: vec_4xi32_splat_eq:
604; ARM78:       @ %bb.0:
605; ARM78-NEXT:    mov r12, sp
606; ARM78-NEXT:    vld1.64 {d16, d17}, [r12]
607; ARM78-NEXT:    vmov d19, r2, r3
608; ARM78-NEXT:    vneg.s32 q8, q8
609; ARM78-NEXT:    vmov d18, r0, r1
610; ARM78-NEXT:    vmov.i32 q10, #0x1
611; ARM78-NEXT:    vshl.u32 q8, q9, q8
612; ARM78-NEXT:    vtst.32 q8, q8, q10
613; ARM78-NEXT:    vmvn q8, q8
614; ARM78-NEXT:    vmovn.i32 d16, q8
615; ARM78-NEXT:    vmov r0, r1, d16
616; ARM78-NEXT:    bx lr
617;
618; THUMB6-LABEL: vec_4xi32_splat_eq:
619; THUMB6:       @ %bb.0:
620; THUMB6-NEXT:    push {r4, r5, r7, lr}
621; THUMB6-NEXT:    ldr r4, [sp, #16]
622; THUMB6-NEXT:    lsrs r0, r4
623; THUMB6-NEXT:    movs r4, #1
624; THUMB6-NEXT:    ands r0, r4
625; THUMB6-NEXT:    rsbs r5, r0, #0
626; THUMB6-NEXT:    adcs r0, r5
627; THUMB6-NEXT:    ldr r5, [sp, #20]
628; THUMB6-NEXT:    lsrs r1, r5
629; THUMB6-NEXT:    ands r1, r4
630; THUMB6-NEXT:    rsbs r5, r1, #0
631; THUMB6-NEXT:    adcs r1, r5
632; THUMB6-NEXT:    ldr r5, [sp, #24]
633; THUMB6-NEXT:    lsrs r2, r5
634; THUMB6-NEXT:    ands r2, r4
635; THUMB6-NEXT:    rsbs r5, r2, #0
636; THUMB6-NEXT:    adcs r2, r5
637; THUMB6-NEXT:    ldr r5, [sp, #28]
638; THUMB6-NEXT:    lsrs r3, r5
639; THUMB6-NEXT:    ands r3, r4
640; THUMB6-NEXT:    rsbs r4, r3, #0
641; THUMB6-NEXT:    adcs r3, r4
642; THUMB6-NEXT:    pop {r4, r5, r7, pc}
643;
644; THUMB78-LABEL: vec_4xi32_splat_eq:
645; THUMB78:       @ %bb.0:
646; THUMB78-NEXT:    mov r12, sp
647; THUMB78-NEXT:    vld1.64 {d16, d17}, [r12]
648; THUMB78-NEXT:    vmov d19, r2, r3
649; THUMB78-NEXT:    vneg.s32 q8, q8
650; THUMB78-NEXT:    vmov d18, r0, r1
651; THUMB78-NEXT:    vmov.i32 q10, #0x1
652; THUMB78-NEXT:    vshl.u32 q8, q9, q8
653; THUMB78-NEXT:    vtst.32 q8, q8, q10
654; THUMB78-NEXT:    vmvn q8, q8
655; THUMB78-NEXT:    vmovn.i32 d16, q8
656; THUMB78-NEXT:    vmov r0, r1, d16
657; THUMB78-NEXT:    bx lr
658  %t0 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
659  %t1 = and <4 x i32> %t0, %x
660  %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
661  ret <4 x i1> %res
662}
663
664define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
665; ARM6-LABEL: vec_4xi32_nonsplat_eq:
666; ARM6:       @ %bb.0:
667; ARM6-NEXT:    ldr r12, [sp, #4]
668; ARM6-NEXT:    mov r0, #1
669; ARM6-NEXT:    bic r1, r0, r1, lsr r12
670; ARM6-NEXT:    ldr r12, [sp, #8]
671; ARM6-NEXT:    mov r0, #65280
672; ARM6-NEXT:    orr r0, r0, #16711680
673; ARM6-NEXT:    and r0, r0, r2, lsr r12
674; ARM6-NEXT:    clz r0, r0
675; ARM6-NEXT:    lsr r2, r0, #5
676; ARM6-NEXT:    ldr r0, [sp, #12]
677; ARM6-NEXT:    mvn r0, r3, lsr r0
678; ARM6-NEXT:    lsr r3, r0, #31
679; ARM6-NEXT:    mov r0, #1
680; ARM6-NEXT:    bx lr
681;
682; ARM78-LABEL: vec_4xi32_nonsplat_eq:
683; ARM78:       @ %bb.0:
684; ARM78-NEXT:    mov r12, sp
685; ARM78-NEXT:    vld1.64 {d16, d17}, [r12]
686; ARM78-NEXT:    adr r12, .LCPI13_0
687; ARM78-NEXT:    vld1.64 {d18, d19}, [r12:128]
688; ARM78-NEXT:    vshl.u32 q8, q9, q8
689; ARM78-NEXT:    vmov d19, r2, r3
690; ARM78-NEXT:    vmov d18, r0, r1
691; ARM78-NEXT:    vtst.32 q8, q8, q9
692; ARM78-NEXT:    vmvn q8, q8
693; ARM78-NEXT:    vmovn.i32 d16, q8
694; ARM78-NEXT:    vmov r0, r1, d16
695; ARM78-NEXT:    bx lr
696; ARM78-NEXT:    .p2align 4
697; ARM78-NEXT:  @ %bb.1:
698; ARM78-NEXT:  .LCPI13_0:
699; ARM78-NEXT:    .long 0 @ 0x0
700; ARM78-NEXT:    .long 1 @ 0x1
701; ARM78-NEXT:    .long 16776960 @ 0xffff00
702; ARM78-NEXT:    .long 2147483648 @ 0x80000000
703;
704; THUMB6-LABEL: vec_4xi32_nonsplat_eq:
705; THUMB6:       @ %bb.0:
706; THUMB6-NEXT:    push {r4, lr}
707; THUMB6-NEXT:    ldr r0, [sp, #12]
708; THUMB6-NEXT:    lsrs r1, r0
709; THUMB6-NEXT:    movs r0, #1
710; THUMB6-NEXT:    ands r1, r0
711; THUMB6-NEXT:    rsbs r4, r1, #0
712; THUMB6-NEXT:    adcs r1, r4
713; THUMB6-NEXT:    ldr r4, [sp, #16]
714; THUMB6-NEXT:    lsrs r2, r4
715; THUMB6-NEXT:    ldr r4, .LCPI13_0
716; THUMB6-NEXT:    ands r4, r2
717; THUMB6-NEXT:    rsbs r2, r4, #0
718; THUMB6-NEXT:    adcs r2, r4
719; THUMB6-NEXT:    ldr r4, [sp, #20]
720; THUMB6-NEXT:    lsrs r3, r4
721; THUMB6-NEXT:    lsls r4, r0, #31
722; THUMB6-NEXT:    ands r4, r3
723; THUMB6-NEXT:    rsbs r3, r4, #0
724; THUMB6-NEXT:    adcs r3, r4
725; THUMB6-NEXT:    pop {r4, pc}
726; THUMB6-NEXT:    .p2align 2
727; THUMB6-NEXT:  @ %bb.1:
728; THUMB6-NEXT:  .LCPI13_0:
729; THUMB6-NEXT:    .long 16776960 @ 0xffff00
730;
731; THUMB78-LABEL: vec_4xi32_nonsplat_eq:
732; THUMB78:       @ %bb.0:
733; THUMB78-NEXT:    mov r12, sp
734; THUMB78-NEXT:    vld1.64 {d16, d17}, [r12]
735; THUMB78-NEXT:    adr.w r12, .LCPI13_0
736; THUMB78-NEXT:    vld1.64 {d18, d19}, [r12:128]
737; THUMB78-NEXT:    vshl.u32 q8, q9, q8
738; THUMB78-NEXT:    vmov d19, r2, r3
739; THUMB78-NEXT:    vmov d18, r0, r1
740; THUMB78-NEXT:    vtst.32 q8, q8, q9
741; THUMB78-NEXT:    vmvn q8, q8
742; THUMB78-NEXT:    vmovn.i32 d16, q8
743; THUMB78-NEXT:    vmov r0, r1, d16
744; THUMB78-NEXT:    bx lr
745; THUMB78-NEXT:    .p2align 4
746; THUMB78-NEXT:  @ %bb.1:
747; THUMB78-NEXT:  .LCPI13_0:
748; THUMB78-NEXT:    .long 0 @ 0x0
749; THUMB78-NEXT:    .long 1 @ 0x1
750; THUMB78-NEXT:    .long 16776960 @ 0xffff00
751; THUMB78-NEXT:    .long 2147483648 @ 0x80000000
752  %t0 = shl <4 x i32> <i32 0, i32 1, i32 16776960, i32 2147483648>, %y
753  %t1 = and <4 x i32> %t0, %x
754  %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
755  ret <4 x i1> %res
756}
757
758define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
759; ARM6-LABEL: vec_4xi32_nonsplat_undef0_eq:
760; ARM6:       @ %bb.0:
761; ARM6-NEXT:    push {r11, lr}
762; ARM6-NEXT:    ldr r2, [sp, #12]
763; ARM6-NEXT:    mov lr, #1
764; ARM6-NEXT:    ldr r12, [sp, #8]
765; ARM6-NEXT:    bic r1, lr, r1, lsr r2
766; ARM6-NEXT:    ldr r2, [sp, #20]
767; ARM6-NEXT:    bic r0, lr, r0, lsr r12
768; ARM6-NEXT:    bic r3, lr, r3, lsr r2
769; ARM6-NEXT:    mov r2, #1
770; ARM6-NEXT:    pop {r11, pc}
771;
772; ARM78-LABEL: vec_4xi32_nonsplat_undef0_eq:
773; ARM78:       @ %bb.0:
774; ARM78-NEXT:    mov r12, sp
775; ARM78-NEXT:    vld1.64 {d16, d17}, [r12]
776; ARM78-NEXT:    vmov d19, r2, r3
777; ARM78-NEXT:    vneg.s32 q8, q8
778; ARM78-NEXT:    vmov d18, r0, r1
779; ARM78-NEXT:    vmov.i32 q10, #0x1
780; ARM78-NEXT:    vshl.u32 q8, q9, q8
781; ARM78-NEXT:    vtst.32 q8, q8, q10
782; ARM78-NEXT:    vmvn q8, q8
783; ARM78-NEXT:    vmovn.i32 d16, q8
784; ARM78-NEXT:    vmov r0, r1, d16
785; ARM78-NEXT:    bx lr
786;
787; THUMB6-LABEL: vec_4xi32_nonsplat_undef0_eq:
788; THUMB6:       @ %bb.0:
789; THUMB6-NEXT:    push {r4, lr}
790; THUMB6-NEXT:    ldr r2, [sp, #8]
791; THUMB6-NEXT:    lsrs r0, r2
792; THUMB6-NEXT:    movs r2, #1
793; THUMB6-NEXT:    ands r0, r2
794; THUMB6-NEXT:    rsbs r4, r0, #0
795; THUMB6-NEXT:    adcs r0, r4
796; THUMB6-NEXT:    ldr r4, [sp, #12]
797; THUMB6-NEXT:    lsrs r1, r4
798; THUMB6-NEXT:    ands r1, r2
799; THUMB6-NEXT:    rsbs r4, r1, #0
800; THUMB6-NEXT:    adcs r1, r4
801; THUMB6-NEXT:    ldr r4, [sp, #20]
802; THUMB6-NEXT:    lsrs r3, r4
803; THUMB6-NEXT:    ands r3, r2
804; THUMB6-NEXT:    rsbs r4, r3, #0
805; THUMB6-NEXT:    adcs r3, r4
806; THUMB6-NEXT:    pop {r4, pc}
807;
808; THUMB78-LABEL: vec_4xi32_nonsplat_undef0_eq:
809; THUMB78:       @ %bb.0:
810; THUMB78-NEXT:    mov r12, sp
811; THUMB78-NEXT:    vld1.64 {d16, d17}, [r12]
812; THUMB78-NEXT:    vmov d19, r2, r3
813; THUMB78-NEXT:    vneg.s32 q8, q8
814; THUMB78-NEXT:    vmov d18, r0, r1
815; THUMB78-NEXT:    vmov.i32 q10, #0x1
816; THUMB78-NEXT:    vshl.u32 q8, q9, q8
817; THUMB78-NEXT:    vtst.32 q8, q8, q10
818; THUMB78-NEXT:    vmvn q8, q8
819; THUMB78-NEXT:    vmovn.i32 d16, q8
820; THUMB78-NEXT:    vmov r0, r1, d16
821; THUMB78-NEXT:    bx lr
822  %t0 = shl <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
823  %t1 = and <4 x i32> %t0, %x
824  %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
825  ret <4 x i1> %res
826}
827define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
828; ARM6-LABEL: vec_4xi32_nonsplat_undef1_eq:
829; ARM6:       @ %bb.0:
830; ARM6-NEXT:    push {r11, lr}
831; ARM6-NEXT:    ldr r2, [sp, #12]
832; ARM6-NEXT:    mov lr, #1
833; ARM6-NEXT:    ldr r12, [sp, #8]
834; ARM6-NEXT:    bic r1, lr, r1, lsr r2
835; ARM6-NEXT:    ldr r2, [sp, #20]
836; ARM6-NEXT:    bic r0, lr, r0, lsr r12
837; ARM6-NEXT:    bic r3, lr, r3, lsr r2
838; ARM6-NEXT:    pop {r11, pc}
839;
840; ARM78-LABEL: vec_4xi32_nonsplat_undef1_eq:
841; ARM78:       @ %bb.0:
842; ARM78-NEXT:    vmov.i32 q8, #0x1
843; ARM78-NEXT:    mov r12, sp
844; ARM78-NEXT:    vld1.64 {d18, d19}, [r12]
845; ARM78-NEXT:    vshl.u32 q8, q8, q9
846; ARM78-NEXT:    vmov d19, r2, r3
847; ARM78-NEXT:    vmov d18, r0, r1
848; ARM78-NEXT:    vtst.32 q8, q8, q9
849; ARM78-NEXT:    vmvn q8, q8
850; ARM78-NEXT:    vmovn.i32 d16, q8
851; ARM78-NEXT:    vmov r0, r1, d16
852; ARM78-NEXT:    bx lr
853;
854; THUMB6-LABEL: vec_4xi32_nonsplat_undef1_eq:
855; THUMB6:       @ %bb.0:
856; THUMB6-NEXT:    push {r4, lr}
857; THUMB6-NEXT:    ldr r2, [sp, #8]
858; THUMB6-NEXT:    lsrs r0, r2
859; THUMB6-NEXT:    movs r2, #1
860; THUMB6-NEXT:    ands r0, r2
861; THUMB6-NEXT:    rsbs r4, r0, #0
862; THUMB6-NEXT:    adcs r0, r4
863; THUMB6-NEXT:    ldr r4, [sp, #12]
864; THUMB6-NEXT:    lsrs r1, r4
865; THUMB6-NEXT:    ands r1, r2
866; THUMB6-NEXT:    rsbs r4, r1, #0
867; THUMB6-NEXT:    adcs r1, r4
868; THUMB6-NEXT:    ldr r4, [sp, #20]
869; THUMB6-NEXT:    lsrs r3, r4
870; THUMB6-NEXT:    ands r3, r2
871; THUMB6-NEXT:    rsbs r2, r3, #0
872; THUMB6-NEXT:    adcs r3, r2
873; THUMB6-NEXT:    pop {r4, pc}
874;
875; THUMB78-LABEL: vec_4xi32_nonsplat_undef1_eq:
876; THUMB78:       @ %bb.0:
877; THUMB78-NEXT:    vmov.i32 q8, #0x1
878; THUMB78-NEXT:    mov r12, sp
879; THUMB78-NEXT:    vld1.64 {d18, d19}, [r12]
880; THUMB78-NEXT:    vshl.u32 q8, q8, q9
881; THUMB78-NEXT:    vmov d19, r2, r3
882; THUMB78-NEXT:    vmov d18, r0, r1
883; THUMB78-NEXT:    vtst.32 q8, q8, q9
884; THUMB78-NEXT:    vmvn q8, q8
885; THUMB78-NEXT:    vmovn.i32 d16, q8
886; THUMB78-NEXT:    vmov r0, r1, d16
887; THUMB78-NEXT:    bx lr
888  %t0 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
889  %t1 = and <4 x i32> %t0, %x
890  %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>
891  ret <4 x i1> %res
892}
893define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
894; ARM6-LABEL: vec_4xi32_nonsplat_undef2_eq:
895; ARM6:       @ %bb.0:
896; ARM6-NEXT:    push {r11, lr}
897; ARM6-NEXT:    ldr r2, [sp, #12]
898; ARM6-NEXT:    mov lr, #1
899; ARM6-NEXT:    ldr r12, [sp, #8]
900; ARM6-NEXT:    bic r1, lr, r1, lsr r2
901; ARM6-NEXT:    ldr r2, [sp, #20]
902; ARM6-NEXT:    bic r0, lr, r0, lsr r12
903; ARM6-NEXT:    bic r3, lr, r3, lsr r2
904; ARM6-NEXT:    pop {r11, pc}
905;
906; ARM78-LABEL: vec_4xi32_nonsplat_undef2_eq:
907; ARM78:       @ %bb.0:
908; ARM78-NEXT:    vmov.i32 q8, #0x1
909; ARM78-NEXT:    mov r12, sp
910; ARM78-NEXT:    vld1.64 {d18, d19}, [r12]
911; ARM78-NEXT:    vshl.u32 q8, q8, q9
912; ARM78-NEXT:    vmov d19, r2, r3
913; ARM78-NEXT:    vmov d18, r0, r1
914; ARM78-NEXT:    vtst.32 q8, q8, q9
915; ARM78-NEXT:    vmvn q8, q8
916; ARM78-NEXT:    vmovn.i32 d16, q8
917; ARM78-NEXT:    vmov r0, r1, d16
918; ARM78-NEXT:    bx lr
919;
920; THUMB6-LABEL: vec_4xi32_nonsplat_undef2_eq:
921; THUMB6:       @ %bb.0:
922; THUMB6-NEXT:    push {r4, lr}
923; THUMB6-NEXT:    ldr r2, [sp, #8]
924; THUMB6-NEXT:    lsrs r0, r2
925; THUMB6-NEXT:    movs r2, #1
926; THUMB6-NEXT:    ands r0, r2
927; THUMB6-NEXT:    rsbs r4, r0, #0
928; THUMB6-NEXT:    adcs r0, r4
929; THUMB6-NEXT:    ldr r4, [sp, #12]
930; THUMB6-NEXT:    lsrs r1, r4
931; THUMB6-NEXT:    ands r1, r2
932; THUMB6-NEXT:    rsbs r4, r1, #0
933; THUMB6-NEXT:    adcs r1, r4
934; THUMB6-NEXT:    ldr r4, [sp, #20]
935; THUMB6-NEXT:    lsrs r3, r4
936; THUMB6-NEXT:    ands r3, r2
937; THUMB6-NEXT:    rsbs r2, r3, #0
938; THUMB6-NEXT:    adcs r3, r2
939; THUMB6-NEXT:    pop {r4, pc}
940;
941; THUMB78-LABEL: vec_4xi32_nonsplat_undef2_eq:
942; THUMB78:       @ %bb.0:
943; THUMB78-NEXT:    vmov.i32 q8, #0x1
944; THUMB78-NEXT:    mov r12, sp
945; THUMB78-NEXT:    vld1.64 {d18, d19}, [r12]
946; THUMB78-NEXT:    vshl.u32 q8, q8, q9
947; THUMB78-NEXT:    vmov d19, r2, r3
948; THUMB78-NEXT:    vmov d18, r0, r1
949; THUMB78-NEXT:    vtst.32 q8, q8, q9
950; THUMB78-NEXT:    vmvn q8, q8
951; THUMB78-NEXT:    vmovn.i32 d16, q8
952; THUMB78-NEXT:    vmov r0, r1, d16
953; THUMB78-NEXT:    bx lr
954  %t0 = shl <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
955  %t1 = and <4 x i32> %t0, %x
956  %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>
957  ret <4 x i1> %res
958}
959
960;------------------------------------------------------------------------------;
961; A special tests
962;------------------------------------------------------------------------------;
963
964define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
965; ARM-LABEL: scalar_i8_signbit_ne:
966; ARM:       @ %bb.0:
967; ARM-NEXT:    uxtb r1, r1
968; ARM-NEXT:    uxtb r0, r0
969; ARM-NEXT:    lsr r0, r0, r1
970; ARM-NEXT:    lsr r0, r0, #7
971; ARM-NEXT:    bx lr
972;
973; THUMB6-LABEL: scalar_i8_signbit_ne:
974; THUMB6:       @ %bb.0:
975; THUMB6-NEXT:    uxtb r1, r1
976; THUMB6-NEXT:    uxtb r0, r0
977; THUMB6-NEXT:    lsrs r0, r1
978; THUMB6-NEXT:    lsrs r0, r0, #7
979; THUMB6-NEXT:    bx lr
980;
981; THUMB7-LABEL: scalar_i8_signbit_ne:
982; THUMB7:       @ %bb.0:
983; THUMB7-NEXT:    uxtb r1, r1
984; THUMB7-NEXT:    uxtb r0, r0
985; THUMB7-NEXT:    lsrs r0, r1
986; THUMB7-NEXT:    lsrs r0, r0, #7
987; THUMB7-NEXT:    bx lr
988;
989; THUMB8-LABEL: scalar_i8_signbit_ne:
990; THUMB8:       @ %bb.0:
991; THUMB8-NEXT:    uxtb r0, r0
992; THUMB8-NEXT:    uxtb r1, r1
993; THUMB8-NEXT:    lsrs r0, r1
994; THUMB8-NEXT:    lsrs r0, r0, #7
995; THUMB8-NEXT:    bx lr
996  %t0 = shl i8 128, %y
997  %t1 = and i8 %t0, %x
998  %res = icmp ne i8 %t1, 0 ;  we are perfectly happy with 'ne' predicate
999  ret i1 %res
1000}
1001
1002;------------------------------------------------------------------------------;
1003; What if X is a constant too?
1004;------------------------------------------------------------------------------;
1005
1006define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
1007; ARM6-LABEL: scalar_i32_x_is_const_eq:
1008; ARM6:       @ %bb.0:
1009; ARM6-NEXT:    ldr r1, .LCPI18_0
1010; ARM6-NEXT:    mov r2, #1
1011; ARM6-NEXT:    bic r0, r2, r1, lsl r0
1012; ARM6-NEXT:    bx lr
1013; ARM6-NEXT:    .p2align 2
1014; ARM6-NEXT:  @ %bb.1:
1015; ARM6-NEXT:  .LCPI18_0:
1016; ARM6-NEXT:    .long 2857740885 @ 0xaa55aa55
1017;
1018; ARM78-LABEL: scalar_i32_x_is_const_eq:
1019; ARM78:       @ %bb.0:
1020; ARM78-NEXT:    movw r1, #43605
1021; ARM78-NEXT:    mov r2, #1
1022; ARM78-NEXT:    movt r1, #43605
1023; ARM78-NEXT:    bic r0, r2, r1, lsl r0
1024; ARM78-NEXT:    bx lr
1025;
1026; THUMB6-LABEL: scalar_i32_x_is_const_eq:
1027; THUMB6:       @ %bb.0:
1028; THUMB6-NEXT:    ldr r1, .LCPI18_0
1029; THUMB6-NEXT:    lsls r1, r0
1030; THUMB6-NEXT:    movs r2, #1
1031; THUMB6-NEXT:    ands r2, r1
1032; THUMB6-NEXT:    rsbs r0, r2, #0
1033; THUMB6-NEXT:    adcs r0, r2
1034; THUMB6-NEXT:    bx lr
1035; THUMB6-NEXT:    .p2align 2
1036; THUMB6-NEXT:  @ %bb.1:
1037; THUMB6-NEXT:  .LCPI18_0:
1038; THUMB6-NEXT:    .long 2857740885 @ 0xaa55aa55
1039;
1040; THUMB78-LABEL: scalar_i32_x_is_const_eq:
1041; THUMB78:       @ %bb.0:
1042; THUMB78-NEXT:    movw r1, #43605
1043; THUMB78-NEXT:    movt r1, #43605
1044; THUMB78-NEXT:    lsl.w r0, r1, r0
1045; THUMB78-NEXT:    movs r1, #1
1046; THUMB78-NEXT:    bic.w r0, r1, r0
1047; THUMB78-NEXT:    bx lr
1048  %t0 = shl i32 2857740885, %y
1049  %t1 = and i32 %t0, 1
1050  %res = icmp eq i32 %t1, 0
1051  ret i1 %res
1052}
1053define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
1054; ARM6-LABEL: scalar_i32_x_is_const2_eq:
1055; ARM6:       @ %bb.0:
1056; ARM6-NEXT:    ldr r2, .LCPI19_0
1057; ARM6-NEXT:    mov r1, #1
1058; ARM6-NEXT:    and r0, r2, r1, lsl r0
1059; ARM6-NEXT:    clz r0, r0
1060; ARM6-NEXT:    lsr r0, r0, #5
1061; ARM6-NEXT:    bx lr
1062; ARM6-NEXT:    .p2align 2
1063; ARM6-NEXT:  @ %bb.1:
1064; ARM6-NEXT:  .LCPI19_0:
1065; ARM6-NEXT:    .long 2857740885 @ 0xaa55aa55
1066;
1067; ARM78-LABEL: scalar_i32_x_is_const2_eq:
1068; ARM78:       @ %bb.0:
1069; ARM78-NEXT:    movw r1, #43605
1070; ARM78-NEXT:    mov r2, #1
1071; ARM78-NEXT:    movt r1, #43605
1072; ARM78-NEXT:    and r0, r1, r2, lsl r0
1073; ARM78-NEXT:    clz r0, r0
1074; ARM78-NEXT:    lsr r0, r0, #5
1075; ARM78-NEXT:    bx lr
1076;
1077; THUMB6-LABEL: scalar_i32_x_is_const2_eq:
1078; THUMB6:       @ %bb.0:
1079; THUMB6-NEXT:    movs r1, #1
1080; THUMB6-NEXT:    lsls r1, r0
1081; THUMB6-NEXT:    ldr r2, .LCPI19_0
1082; THUMB6-NEXT:    ands r2, r1
1083; THUMB6-NEXT:    rsbs r0, r2, #0
1084; THUMB6-NEXT:    adcs r0, r2
1085; THUMB6-NEXT:    bx lr
1086; THUMB6-NEXT:    .p2align 2
1087; THUMB6-NEXT:  @ %bb.1:
1088; THUMB6-NEXT:  .LCPI19_0:
1089; THUMB6-NEXT:    .long 2857740885 @ 0xaa55aa55
1090;
1091; THUMB78-LABEL: scalar_i32_x_is_const2_eq:
1092; THUMB78:       @ %bb.0:
1093; THUMB78-NEXT:    movs r1, #1
1094; THUMB78-NEXT:    lsl.w r0, r1, r0
1095; THUMB78-NEXT:    movw r1, #43605
1096; THUMB78-NEXT:    movt r1, #43605
1097; THUMB78-NEXT:    ands r0, r1
1098; THUMB78-NEXT:    clz r0, r0
1099; THUMB78-NEXT:    lsrs r0, r0, #5
1100; THUMB78-NEXT:    bx lr
1101  %t0 = shl i32 1, %y
1102  %t1 = and i32 %t0, 2857740885
1103  %res = icmp eq i32 %t1, 0
1104  ret i1 %res
1105}
1106
1107;------------------------------------------------------------------------------;
1108; A few negative tests
1109;------------------------------------------------------------------------------;
1110
1111define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
1112; ARM6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1113; ARM6:       @ %bb.0:
1114; ARM6-NEXT:    uxtb r1, r1
1115; ARM6-NEXT:    mov r2, #24
1116; ARM6-NEXT:    and r0, r0, r2, lsl r1
1117; ARM6-NEXT:    sxtb r1, r0
1118; ARM6-NEXT:    mov r0, #0
1119; ARM6-NEXT:    cmp r1, #0
1120; ARM6-NEXT:    movmi r0, #1
1121; ARM6-NEXT:    bx lr
1122;
1123; ARM78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1124; ARM78:       @ %bb.0:
1125; ARM78-NEXT:    uxtb r1, r1
1126; ARM78-NEXT:    mov r2, #24
1127; ARM78-NEXT:    and r0, r0, r2, lsl r1
1128; ARM78-NEXT:    sxtb r1, r0
1129; ARM78-NEXT:    mov r0, #0
1130; ARM78-NEXT:    cmp r1, #0
1131; ARM78-NEXT:    movwmi r0, #1
1132; ARM78-NEXT:    bx lr
1133;
1134; THUMB6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1135; THUMB6:       @ %bb.0:
1136; THUMB6-NEXT:    uxtb r1, r1
1137; THUMB6-NEXT:    movs r2, #24
1138; THUMB6-NEXT:    lsls r2, r1
1139; THUMB6-NEXT:    ands r2, r0
1140; THUMB6-NEXT:    sxtb r0, r2
1141; THUMB6-NEXT:    cmp r0, #0
1142; THUMB6-NEXT:    bmi .LBB20_2
1143; THUMB6-NEXT:  @ %bb.1:
1144; THUMB6-NEXT:    movs r0, #0
1145; THUMB6-NEXT:    bx lr
1146; THUMB6-NEXT:  .LBB20_2:
1147; THUMB6-NEXT:    movs r0, #1
1148; THUMB6-NEXT:    bx lr
1149;
1150; THUMB78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1151; THUMB78:       @ %bb.0:
1152; THUMB78-NEXT:    uxtb r1, r1
1153; THUMB78-NEXT:    movs r2, #24
1154; THUMB78-NEXT:    lsl.w r1, r2, r1
1155; THUMB78-NEXT:    ands r0, r1
1156; THUMB78-NEXT:    sxtb r1, r0
1157; THUMB78-NEXT:    movs r0, #0
1158; THUMB78-NEXT:    cmp r1, #0
1159; THUMB78-NEXT:    it mi
1160; THUMB78-NEXT:    movmi r0, #1
1161; THUMB78-NEXT:    bx lr
1162  %t0 = shl i8 24, %y
1163  %t1 = and i8 %t0, %x
1164  %res = icmp slt i8 %t1, 0
1165  ret i1 %res
1166}
1167
1168define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
1169; ARM-LABEL: scalar_i8_signbit_eq_with_nonzero:
1170; ARM:       @ %bb.0:
1171; ARM-NEXT:    mov r0, #0
1172; ARM-NEXT:    bx lr
1173;
1174; THUMB6-LABEL: scalar_i8_signbit_eq_with_nonzero:
1175; THUMB6:       @ %bb.0:
1176; THUMB6-NEXT:    uxtb r1, r1
1177; THUMB6-NEXT:    movs r2, #127
1178; THUMB6-NEXT:    mvns r2, r2
1179; THUMB6-NEXT:    lsls r2, r1
1180; THUMB6-NEXT:    ands r2, r0
1181; THUMB6-NEXT:    uxtb r0, r2
1182; THUMB6-NEXT:    subs r1, r0, #1
1183; THUMB6-NEXT:    rsbs r0, r1, #0
1184; THUMB6-NEXT:    adcs r0, r1
1185; THUMB6-NEXT:    bx lr
1186;
1187; THUMB78-LABEL: scalar_i8_signbit_eq_with_nonzero:
1188; THUMB78:       @ %bb.0:
1189; THUMB78-NEXT:    movs r0, #0
1190; THUMB78-NEXT:    bx lr
1191  %t0 = shl i8 128, %y
1192  %t1 = and i8 %t0, %x
1193  %res = icmp eq i8 %t1, 1 ; should be comparing with 0
1194  ret i1 %res
1195}
1196