1; RUN: llc -mtriple=armv7--eabi -verify-machineinstrs < %s | FileCheck %s 2 3; Check the way we schedule/merge a bunch of loads and stores. 4; Originally test/CodeGen/ARM/2011-07-07-ScheduleDAGCrash.ll ; now 5; being used as a test of optimizations related to ldm/stm. 6 7; FIXME: We could merge more loads/stores with regalloc hints. 8; FIXME: Fix scheduling so we don't have 16 live registers. 9 10define void @f(i256* nocapture %a, i256* nocapture %b, i256* nocapture %cc, i256* nocapture %dd) nounwind uwtable noinline ssp { 11entry: 12 %c = load i256, i256* %cc 13 %d = load i256, i256* %dd 14 %add = add nsw i256 %c, %d 15 store i256 %add, i256* %a, align 8 16 %or = or i256 %c, 1606938044258990275541962092341162602522202993782792835301376 17 %add6 = add nsw i256 %or, %d 18 store i256 %add6, i256* %b, align 8 19 ret void 20 ; CHECK-DAG: ldm r2 21 ; CHECK-DAG: ldr {{.*}}, [r3] 22 ; CHECK-DAG: ldr {{.*}}, [r3, #4] 23 ; CHECK-DAG: ldr {{.*}}, [r3, #8] 24 ; CHECK-DAG: ldr {{.*}}, [r3, #12] 25 ; CHECK-DAG: ldr {{.*}}, [r3, #16] 26 ; CHECK-DAG: ldr {{.*}}, [r3, #20] 27 ; CHECK-DAG: ldr {{.*}}, [r3, #24] 28 ; CHECK-DAG: ldr {{.*}}, [r3, #28] 29 ; CHECK-DAG: ldr {{.*}}, [r2, #20] 30 ; CHECK-DAG: ldr {{.*}}, [r2, #24] 31 ; CHECK-DAG: ldr {{.*}}, [r2, #28] 32 ; CHECK-DAG: stm r0 33 ; CHECK-DAG: str {{.*}}, [r0, #20] 34 ; CHECK-DAG: str {{.*}}, [r0, #24] 35 ; CHECK-DAG: str {{.*}}, [r0, #28] 36 ; CHECK-DAG: stm r1 37 ; CHECK-DAG: str {{.*}}, [r1, #20] 38 ; CHECK-DAG: str {{.*}}, [r1, #24] 39 ; CHECK-DAG: str {{.*}}, [r1, #28] 40} 41