1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -O0 -mtriple=armebv7 -target-abi apcs -o - %s | FileCheck %s 3 4@vec6_p = external global <6 x i16> 5 6define i32 @vec_to_int() { 7; CHECK-LABEL: vec_to_int: 8; CHECK: @ %bb.0: @ %bb.0 9; CHECK-NEXT: push {r4} 10; CHECK-NEXT: sub sp, sp, #28 11; CHECK-NEXT: movw r0, :lower16:vec6_p 12; CHECK-NEXT: movt r0, :upper16:vec6_p 13; CHECK-NEXT: vld1.8 {d16}, [r0]! 14; CHECK-NEXT: ldr r0, [r0] 15; CHECK-NEXT: @ implicit-def: $d17 16; CHECK-NEXT: vmov.32 d17[0], r0 17; CHECK-NEXT: vrev32.16 d18, d17 18; CHECK-NEXT: vrev16.8 d16, d16 19; CHECK-NEXT: @ kill: def $d16 killed $d16 def $q8 20; CHECK-NEXT: vmov.f64 d17, d18 21; CHECK-NEXT: vstmia sp, {d16, d17} @ 16-byte Spill 22; CHECK-NEXT: b .LBB0_1 23; CHECK-NEXT: .LBB0_1: @ %bb.1 24; CHECK-NEXT: vldmia sp, {d16, d17} @ 16-byte Reload 25; CHECK-NEXT: vrev32.16 q8, q8 26; CHECK-NEXT: vmov.f64 d16, d17 27; CHECK-NEXT: vmov.32 r0, d16[0] 28; CHECK-NEXT: add sp, sp, #28 29; CHECK-NEXT: pop {r4} 30; CHECK-NEXT: bx lr 31bb.0: 32 %vec6 = load <6 x i16>, <6 x i16>* @vec6_p, align 1 33 br label %bb.1 34 35bb.1: 36 %0 = bitcast <6 x i16> %vec6 to i96 37 %1 = trunc i96 %0 to i32 38 ret i32 %1 39} 40 41define i16 @int_to_vec(i80 %in) { 42; CHECK-LABEL: int_to_vec: 43; CHECK: @ %bb.0: 44; CHECK-NEXT: @ kill: def $r2 killed $r1 45; CHECK-NEXT: @ kill: def $r2 killed $r0 46; CHECK-NEXT: lsl r0, r0, #16 47; CHECK-NEXT: orr r0, r0, r1, lsr #16 48; CHECK-NEXT: @ implicit-def: $d18 49; CHECK-NEXT: vmov.32 d18[0], r0 50; CHECK-NEXT: @ implicit-def: $q8 51; CHECK-NEXT: vmov.f64 d16, d18 52; CHECK-NEXT: vrev32.16 q8, q8 53; CHECK-NEXT: @ kill: def $d16 killed $d16 killed $q8 54; CHECK-NEXT: vmov.u16 r0, d16[0] 55; CHECK-NEXT: bx lr 56 %vec = bitcast i80 %in to <5 x i16> 57 %e0 = extractelement <5 x i16> %vec, i32 0 58 ret i16 %e0 59} 60