1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=thumbv7-- -run-pass=machine-outliner -verify-machineinstrs \ 3# RUN: %s -o - | FileCheck %s 4 5--- | 6 define void @dont_outline_asm() #0 { ret void } 7 define void @dont_outline_lr() #0 { ret void } 8 define void @dont_outline_lr2() #0 { ret void } 9 define void @dont_outline_it() #0 { ret void } 10 define void @dont_outline_pic() #0 { ret void } 11 define void @dont_outline_mve() #0 { ret void } 12 declare void @z(i32, i32, i32, i32) 13 14 attributes #0 = { minsize optsize } 15... 16--- 17 18name: dont_outline_asm 19tracksRegLiveness: true 20body: | 21 ; CHECK-LABEL: name: dont_outline_asm 22 ; CHECK: bb.0: 23 ; CHECK: INLINEASM &"movs r0, #42", 1 24 ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0 25 ; CHECK: bb.1: 26 ; CHECK: INLINEASM &"movs r0, #42", 1 27 ; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0 28 bb.0: 29 INLINEASM &"movs r0, #42", 1 30 $r0, dead $cpsr = tMOVi8 1, 14, $noreg 31 $r1, dead $cpsr = tMOVi8 1, 14, $noreg 32 $r2, dead $cpsr = tMOVi8 1, 14, $noreg 33 $r3, dead $cpsr = tMOVi8 1, 14, $noreg 34 tBL 14, $noreg, @z 35 bb.1: 36 INLINEASM &"movs r0, #42", 1 37 $r0, dead $cpsr = tMOVi8 1, 14, $noreg 38 $r1, dead $cpsr = tMOVi8 1, 14, $noreg 39 $r2, dead $cpsr = tMOVi8 1, 14, $noreg 40 $r3, dead $cpsr = tMOVi8 1, 14, $noreg 41 tBL 14, $noreg, @z 42 bb.2: 43 tBX_RET 14, $noreg 44... 45--- 46 47name: dont_outline_lr 48tracksRegLiveness: true 49body: | 50 ; CHECK-LABEL: name: dont_outline_lr 51 ; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION 52 bb.0: 53 liveins: $lr 54 $r0 = tMOVr $lr, 14, $noreg 55 $r1 = tMOVr $lr, 14, $noreg 56 $r2 = tMOVr $lr, 14, $noreg 57 $r3 = tMOVr $lr, 14, $noreg 58 tBL 14, $noreg, @z 59 bb.1: 60 liveins: $lr 61 $r0 = tMOVr $lr, 14, $noreg 62 $r1 = tMOVr $lr, 14, $noreg 63 $r2 = tMOVr $lr, 14, $noreg 64 $r3 = tMOVr $lr, 14, $noreg 65 tBL 14, $noreg, @z 66 bb.2: 67 tBX_RET 14, $noreg 68... 69--- 70 71name: dont_outline_lr2 72tracksRegLiveness: true 73body: | 74 ; CHECK-LABEL: name: dont_outline_lr2 75 ; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION 76 bb.0: 77 liveins: $r0 78 $lr = tMOVr $r0, 14, $noreg 79 $r1 = tMOVr $r0, 14, $noreg 80 $r2 = tMOVr $r0, 14, $noreg 81 $r3 = tMOVr $r0, 14, $noreg 82 $r4 = tMOVr $r0, 14, $noreg 83 tBLXr 14, $lr, $noreg 84 bb.1: 85 liveins: $r0 86 $lr = tMOVr $r0, 14, $noreg 87 $r1 = tMOVr $r0, 14, $noreg 88 $r2 = tMOVr $r0, 14, $noreg 89 $r3 = tMOVr $r0, 14, $noreg 90 $r4 = tMOVr $r0, 14, $noreg 91 tBLXr 14, $lr, $noreg 92 bb.2: 93 tBX_RET 14, $noreg 94... 95--- 96 97name: dont_outline_it 98tracksRegLiveness: true 99body: | 100 ; CHECK-LABEL: name: dont_outline_it 101 ; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION 102 bb.0: 103 t2IT 0, 1, implicit-def $itstate 104 $r0, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate 105 $r1, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate 106 $r2, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate 107 $r3, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate 108 tBL 14, $noreg, @z 109 bb.1: 110 t2IT 0, 1, implicit-def $itstate 111 $r0, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate 112 $r1, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate 113 $r2, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate 114 $r3, dead $cpsr = tMOVi8 1, 0, $noreg, implicit $itstate 115 tBL 14, $noreg, @z 116 bb.2: 117 tBX_RET 14, $noreg 118... 119--- 120 121name: dont_outline_pic 122tracksRegLiveness: true 123body: | 124 ; CHECK-LABEL: name: dont_outline_pic 125 ; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION 126 bb.0: 127 $r0 = t2MOVi16_ga_pcrel target-flags(arm-lo16, arm-nonlazy) @z, 0 128 $r0 = t2MOVTi16_ga_pcrel $r0, target-flags(arm-lo16, arm-nonlazy) @z, 0 129 $r0 = PICADD $r0, 1, 14, $noreg 130 $r1 = PICLDR $r0, 2, 14, $noreg 131 PICSTR $r0, $r1, 3, 14, $noreg 132 tBL 14, $noreg, @z 133 bb.1: 134 $r0 = t2MOVi16_ga_pcrel target-flags(arm-lo16, arm-nonlazy) @z, 0 135 $r0 = t2MOVTi16_ga_pcrel $r0, target-flags(arm-lo16, arm-nonlazy) @z, 0 136 $r0 = PICADD $r0, 1, 14, $noreg 137 $r1 = PICLDR $r0, 2, 14, $noreg 138 PICSTR $r0, $r1, 3, 14, $noreg 139 tBL 14, $noreg, @z 140 bb.2: 141 tBX_RET 14, $noreg 142... 143--- 144 145name: dont_outline_mve 146tracksRegLiveness: true 147body: | 148 ; CHECK-LABEL: name: dont_outline_mve 149 ; CHECK-NOT: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION 150 bb.0: 151 liveins: $r3, $r4, $q0, $q3, $q4, $q5 152 $q5 = MVE_VDUP32 $r3, 0, $noreg, $q5 153 $q4 = MVE_VDUP32 $r4, 0, $noreg, $q4 154 $q0 = MVE_VADDf32 $q4, $q5, 0, $noreg, $q0 155 $lr = t2DoLoopStart $r4 156 $r0 = MVE_VMOV_from_lane_32 renamable $q0, 1, 14, $noreg 157 tBL 14, $noreg, @z 158 bb.1: 159 liveins: $r3, $r4, $q0, $q3, $q4, $q5 160 $q5 = MVE_VDUP32 $r3, 0, $noreg, $q5 161 $q4 = MVE_VDUP32 $r4, 0, $noreg, $q4 162 $q0 = MVE_VADDf32 $q4, $q5, 0, $noreg, $q0 163 $lr = t2DoLoopStart $r4 164 $r0 = MVE_VMOV_from_lane_32 renamable $q0, 1, 14, $noreg 165 tBL 14, $noreg, @z 166 bb.2: 167 tBX_RET 14, $noreg 168