1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s 3; Test that we correctly align elements when using va_arg 4 5define i64 @test1(i32 %i, ...) nounwind optsize { 6; CHECK-LABEL: test1: 7; CHECK: @ %bb.0: @ %entry 8; CHECK-NEXT: .pad #12 9; CHECK-NEXT: sub sp, sp, #12 10; CHECK-NEXT: .pad #4 11; CHECK-NEXT: sub sp, sp, #4 12; CHECK-NEXT: add r0, sp, #4 13; CHECK-NEXT: stmib sp, {r1, r2, r3} 14; CHECK-NEXT: add r0, r0, #7 15; CHECK-NEXT: bic r1, r0, #7 16; CHECK-NEXT: orr r0, r1, #4 17; CHECK-NEXT: str r0, [sp] 18; CHECK-NEXT: ldr r0, [r1] 19; CHECK-NEXT: add r2, r1, #8 20; CHECK-NEXT: str r2, [sp] 21; CHECK-NEXT: ldr r1, [r1, #4] 22; CHECK-NEXT: add sp, sp, #4 23; CHECK-NEXT: add sp, sp, #12 24; CHECK-NEXT: bx lr 25entry: 26 %g = alloca i8*, align 4 27 %g1 = bitcast i8** %g to i8* 28 call void @llvm.va_start(i8* %g1) 29 %0 = va_arg i8** %g, i64 30 call void @llvm.va_end(i8* %g1) 31 ret i64 %0 32} 33 34define double @test2(i32 %a, i32* %b, ...) nounwind optsize { 35; CHECK-LABEL: test2: 36; CHECK: @ %bb.0: @ %entry 37; CHECK-NEXT: .pad #8 38; CHECK-NEXT: sub sp, sp, #8 39; CHECK-NEXT: .pad #4 40; CHECK-NEXT: sub sp, sp, #4 41; CHECK-NEXT: add r0, sp, #4 42; CHECK-NEXT: stmib sp, {r2, r3} 43; CHECK-NEXT: add r0, r0, #11 44; CHECK-NEXT: bic r0, r0, #3 45; CHECK-NEXT: str r2, [r1] 46; CHECK-NEXT: add r1, r0, #8 47; CHECK-NEXT: str r1, [sp] 48; CHECK-NEXT: vldr d16, [r0] 49; CHECK-NEXT: vmov r0, r1, d16 50; CHECK-NEXT: add sp, sp, #4 51; CHECK-NEXT: add sp, sp, #8 52; CHECK-NEXT: bx lr 53entry: 54 %ap = alloca i8*, align 4 ; <i8**> [#uses=3] 55 %ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=2] 56 call void @llvm.va_start(i8* %ap1) 57 %0 = va_arg i8** %ap, i32 ; <i32> [#uses=0] 58 store i32 %0, i32* %b 59 %1 = va_arg i8** %ap, double ; <double> [#uses=1] 60 call void @llvm.va_end(i8* %ap1) 61 ret double %1 62} 63 64 65declare void @llvm.va_start(i8*) nounwind 66 67declare void @llvm.va_end(i8*) nounwind 68