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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=arm-none-eabi -mattr=-neon | FileCheck %s --check-prefix=CHECK
3
4declare half @llvm.vector.reduce.fadd.f16.v4f16(half, <4 x half>)
5declare float @llvm.vector.reduce.fadd.f32.v4f32(float, <4 x float>)
6declare double @llvm.vector.reduce.fadd.f64.v2f64(double, <2 x double>)
7declare fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128, <2 x fp128>)
8
9define half @test_v4f16_reassoc(<4 x half> %a) nounwind {
10; CHECK-LABEL: test_v4f16_reassoc:
11; CHECK:       @ %bb.0:
12; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, lr}
13; CHECK-NEXT:    push {r4, r5, r6, r7, r8, lr}
14; CHECK-NEXT:    mov r4, #255
15; CHECK-NEXT:    mov r7, r0
16; CHECK-NEXT:    orr r4, r4, #65280
17; CHECK-NEXT:    mov r5, r2
18; CHECK-NEXT:    and r0, r3, r4
19; CHECK-NEXT:    mov r6, r1
20; CHECK-NEXT:    bl __aeabi_h2f
21; CHECK-NEXT:    mov r8, r0
22; CHECK-NEXT:    and r0, r5, r4
23; CHECK-NEXT:    bl __aeabi_h2f
24; CHECK-NEXT:    mov r5, r0
25; CHECK-NEXT:    and r0, r7, r4
26; CHECK-NEXT:    bl __aeabi_h2f
27; CHECK-NEXT:    mov r7, r0
28; CHECK-NEXT:    and r0, r6, r4
29; CHECK-NEXT:    bl __aeabi_h2f
30; CHECK-NEXT:    mov r1, r0
31; CHECK-NEXT:    mov r0, r7
32; CHECK-NEXT:    bl __aeabi_fadd
33; CHECK-NEXT:    mov r1, r5
34; CHECK-NEXT:    bl __aeabi_fadd
35; CHECK-NEXT:    mov r1, r8
36; CHECK-NEXT:    bl __aeabi_fadd
37; CHECK-NEXT:    bl __aeabi_f2h
38; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, lr}
39; CHECK-NEXT:    mov pc, lr
40  %b = call reassoc half @llvm.vector.reduce.fadd.f16.v4f16(half -0.0, <4 x half> %a)
41  ret half %b
42}
43
44define half @test_v4f16_seq(<4 x half> %a) nounwind {
45; CHECK-LABEL: test_v4f16_seq:
46; CHECK:       @ %bb.0:
47; CHECK-NEXT:    .save {r4, r5, r6, r7, r8, lr}
48; CHECK-NEXT:    push {r4, r5, r6, r7, r8, lr}
49; CHECK-NEXT:    mov r4, #255
50; CHECK-NEXT:    mov r7, r0
51; CHECK-NEXT:    orr r4, r4, #65280
52; CHECK-NEXT:    mov r5, r2
53; CHECK-NEXT:    and r0, r3, r4
54; CHECK-NEXT:    mov r6, r1
55; CHECK-NEXT:    bl __aeabi_h2f
56; CHECK-NEXT:    mov r8, r0
57; CHECK-NEXT:    and r0, r5, r4
58; CHECK-NEXT:    bl __aeabi_h2f
59; CHECK-NEXT:    mov r5, r0
60; CHECK-NEXT:    and r0, r7, r4
61; CHECK-NEXT:    bl __aeabi_h2f
62; CHECK-NEXT:    mov r7, r0
63; CHECK-NEXT:    and r0, r6, r4
64; CHECK-NEXT:    bl __aeabi_h2f
65; CHECK-NEXT:    mov r1, r0
66; CHECK-NEXT:    mov r0, r7
67; CHECK-NEXT:    bl __aeabi_fadd
68; CHECK-NEXT:    mov r1, r5
69; CHECK-NEXT:    bl __aeabi_fadd
70; CHECK-NEXT:    mov r1, r8
71; CHECK-NEXT:    bl __aeabi_fadd
72; CHECK-NEXT:    bl __aeabi_f2h
73; CHECK-NEXT:    pop {r4, r5, r6, r7, r8, lr}
74; CHECK-NEXT:    mov pc, lr
75  %b = call half @llvm.vector.reduce.fadd.f16.v4f16(half -0.0, <4 x half> %a)
76  ret half %b
77}
78
79define float @test_v4f32_reassoc(<4 x float> %a) nounwind {
80; CHECK-LABEL: test_v4f32_reassoc:
81; CHECK:       @ %bb.0:
82; CHECK-NEXT:    .save {r4, r5, r11, lr}
83; CHECK-NEXT:    push {r4, r5, r11, lr}
84; CHECK-NEXT:    mov r4, r3
85; CHECK-NEXT:    mov r5, r2
86; CHECK-NEXT:    bl __aeabi_fadd
87; CHECK-NEXT:    mov r1, r5
88; CHECK-NEXT:    bl __aeabi_fadd
89; CHECK-NEXT:    mov r1, r4
90; CHECK-NEXT:    bl __aeabi_fadd
91; CHECK-NEXT:    pop {r4, r5, r11, lr}
92; CHECK-NEXT:    mov pc, lr
93  %b = call reassoc float @llvm.vector.reduce.fadd.f32.v4f32(float -0.0, <4 x float> %a)
94  ret float %b
95}
96
97define float @test_v4f32_seq(<4 x float> %a) nounwind {
98; CHECK-LABEL: test_v4f32_seq:
99; CHECK:       @ %bb.0:
100; CHECK-NEXT:    .save {r4, r5, r11, lr}
101; CHECK-NEXT:    push {r4, r5, r11, lr}
102; CHECK-NEXT:    mov r4, r3
103; CHECK-NEXT:    mov r5, r2
104; CHECK-NEXT:    bl __aeabi_fadd
105; CHECK-NEXT:    mov r1, r5
106; CHECK-NEXT:    bl __aeabi_fadd
107; CHECK-NEXT:    mov r1, r4
108; CHECK-NEXT:    bl __aeabi_fadd
109; CHECK-NEXT:    pop {r4, r5, r11, lr}
110; CHECK-NEXT:    mov pc, lr
111  %b = call float @llvm.vector.reduce.fadd.f32.v4f32(float -0.0, <4 x float> %a)
112  ret float %b
113}
114
115define double @test_v2f64_reassoc(<2 x double> %a) nounwind {
116; CHECK-LABEL: test_v2f64_reassoc:
117; CHECK:       @ %bb.0:
118; CHECK-NEXT:    .save {r11, lr}
119; CHECK-NEXT:    push {r11, lr}
120; CHECK-NEXT:    bl __aeabi_dadd
121; CHECK-NEXT:    pop {r11, lr}
122; CHECK-NEXT:    mov pc, lr
123  %b = call reassoc double @llvm.vector.reduce.fadd.f64.v2f64(double -0.0, <2 x double> %a)
124  ret double %b
125}
126
127define double @test_v2f64_seq(<2 x double> %a) nounwind {
128; CHECK-LABEL: test_v2f64_seq:
129; CHECK:       @ %bb.0:
130; CHECK-NEXT:    .save {r11, lr}
131; CHECK-NEXT:    push {r11, lr}
132; CHECK-NEXT:    bl __aeabi_dadd
133; CHECK-NEXT:    pop {r11, lr}
134; CHECK-NEXT:    mov pc, lr
135  %b = call double @llvm.vector.reduce.fadd.f64.v2f64(double -0.0, <2 x double> %a)
136  ret double %b
137}
138
139define fp128 @test_v2f128_reassoc(<2 x fp128> %a) nounwind {
140; CHECK-LABEL: test_v2f128_reassoc:
141; CHECK:       @ %bb.0:
142; CHECK-NEXT:    .save {r11, lr}
143; CHECK-NEXT:    push {r11, lr}
144; CHECK-NEXT:    .pad #16
145; CHECK-NEXT:    sub sp, sp, #16
146; CHECK-NEXT:    ldr r12, [sp, #36]
147; CHECK-NEXT:    str r12, [sp, #12]
148; CHECK-NEXT:    ldr r12, [sp, #32]
149; CHECK-NEXT:    str r12, [sp, #8]
150; CHECK-NEXT:    ldr r12, [sp, #28]
151; CHECK-NEXT:    str r12, [sp, #4]
152; CHECK-NEXT:    ldr r12, [sp, #24]
153; CHECK-NEXT:    str r12, [sp]
154; CHECK-NEXT:    bl __addtf3
155; CHECK-NEXT:    add sp, sp, #16
156; CHECK-NEXT:    pop {r11, lr}
157; CHECK-NEXT:    mov pc, lr
158  %b = call reassoc fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 0xL00000000000000008000000000000000, <2 x fp128> %a)
159  ret fp128 %b
160}
161
162define fp128 @test_v2f128_seq(<2 x fp128> %a) nounwind {
163; CHECK-LABEL: test_v2f128_seq:
164; CHECK:       @ %bb.0:
165; CHECK-NEXT:    .save {r11, lr}
166; CHECK-NEXT:    push {r11, lr}
167; CHECK-NEXT:    .pad #16
168; CHECK-NEXT:    sub sp, sp, #16
169; CHECK-NEXT:    ldr r12, [sp, #36]
170; CHECK-NEXT:    str r12, [sp, #12]
171; CHECK-NEXT:    ldr r12, [sp, #32]
172; CHECK-NEXT:    str r12, [sp, #8]
173; CHECK-NEXT:    ldr r12, [sp, #28]
174; CHECK-NEXT:    str r12, [sp, #4]
175; CHECK-NEXT:    ldr r12, [sp, #24]
176; CHECK-NEXT:    str r12, [sp]
177; CHECK-NEXT:    bl __addtf3
178; CHECK-NEXT:    add sp, sp, #16
179; CHECK-NEXT:    pop {r11, lr}
180; CHECK-NEXT:    mov pc, lr
181  %b = call fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 0xL00000000000000008000000000000000, <2 x fp128> %a)
182  ret fp128 %b
183}
184