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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+neon | FileCheck %s --check-prefix=CHECK
3
4declare half @llvm.vector.reduce.fmul.f16.v1f16(half, <1 x half>)
5declare float @llvm.vector.reduce.fmul.f32.v1f32(float, <1 x float>)
6declare double @llvm.vector.reduce.fmul.f64.v1f64(double, <1 x double>)
7declare fp128 @llvm.vector.reduce.fmul.f128.v1f128(fp128, <1 x fp128>)
8
9declare float @llvm.vector.reduce.fmul.f32.v3f32(float, <3 x float>)
10declare fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128, <2 x fp128>)
11declare float @llvm.vector.reduce.fmul.f32.v16f32(float, <16 x float>)
12
13define half @test_v1f16(<1 x half> %a) nounwind {
14; CHECK-LABEL: test_v1f16:
15; CHECK:       @ %bb.0:
16; CHECK-NEXT:    .save {r11, lr}
17; CHECK-NEXT:    push {r11, lr}
18; CHECK-NEXT:    bl __aeabi_f2h
19; CHECK-NEXT:    mov r1, #255
20; CHECK-NEXT:    orr r1, r1, #65280
21; CHECK-NEXT:    and r0, r0, r1
22; CHECK-NEXT:    pop {r11, lr}
23; CHECK-NEXT:    mov pc, lr
24  %b = call half @llvm.vector.reduce.fmul.f16.v1f16(half 1.0, <1 x half> %a)
25  ret half %b
26}
27
28define float @test_v1f32(<1 x float> %a) nounwind {
29; CHECK-LABEL: test_v1f32:
30; CHECK:       @ %bb.0:
31; CHECK-NEXT:    mov pc, lr
32  %b = call float @llvm.vector.reduce.fmul.f32.v1f32(float 1.0, <1 x float> %a)
33  ret float %b
34}
35
36define double @test_v1f64(<1 x double> %a) nounwind {
37; CHECK-LABEL: test_v1f64:
38; CHECK:       @ %bb.0:
39; CHECK-NEXT:    mov pc, lr
40  %b = call double @llvm.vector.reduce.fmul.f64.v1f64(double 1.0, <1 x double> %a)
41  ret double %b
42}
43
44define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
45; CHECK-LABEL: test_v1f128:
46; CHECK:       @ %bb.0:
47; CHECK-NEXT:    mov pc, lr
48  %b = call fp128 @llvm.vector.reduce.fmul.f128.v1f128(fp128 0xL00000000000000003fff00000000000000, <1 x fp128> %a)
49  ret fp128 %b
50}
51
52define float @test_v3f32(<3 x float> %a) nounwind {
53; CHECK-LABEL: test_v3f32:
54; CHECK:       @ %bb.0:
55; CHECK-NEXT:    vmov d1, r2, r3
56; CHECK-NEXT:    vmov d0, r0, r1
57; CHECK-NEXT:    vmul.f32 s4, s0, s1
58; CHECK-NEXT:    vmul.f32 s0, s4, s2
59; CHECK-NEXT:    vmov r0, s0
60; CHECK-NEXT:    mov pc, lr
61  %b = call float @llvm.vector.reduce.fmul.f32.v3f32(float 1.0, <3 x float> %a)
62  ret float %b
63}
64
65define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
66; CHECK-LABEL: test_v2f128:
67; CHECK:       @ %bb.0:
68; CHECK-NEXT:    .save {r4, r5, r11, lr}
69; CHECK-NEXT:    push {r4, r5, r11, lr}
70; CHECK-NEXT:    .pad #16
71; CHECK-NEXT:    sub sp, sp, #16
72; CHECK-NEXT:    ldr r12, [sp, #36]
73; CHECK-NEXT:    ldr lr, [sp, #32]
74; CHECK-NEXT:    ldr r4, [sp, #40]
75; CHECK-NEXT:    ldr r5, [sp, #44]
76; CHECK-NEXT:    str lr, [sp]
77; CHECK-NEXT:    str r12, [sp, #4]
78; CHECK-NEXT:    str r4, [sp, #8]
79; CHECK-NEXT:    str r5, [sp, #12]
80; CHECK-NEXT:    bl __multf3
81; CHECK-NEXT:    add sp, sp, #16
82; CHECK-NEXT:    pop {r4, r5, r11, lr}
83; CHECK-NEXT:    mov pc, lr
84  %b = call fp128 @llvm.vector.reduce.fmul.f128.v2f128(fp128 0xL00000000000000003fff00000000000000, <2 x fp128> %a)
85  ret fp128 %b
86}
87
88define float @test_v16f32(<16 x float> %a) nounwind {
89; CHECK-LABEL: test_v16f32:
90; CHECK:       @ %bb.0:
91; CHECK-NEXT:    vmov d1, r2, r3
92; CHECK-NEXT:    vmov d0, r0, r1
93; CHECK-NEXT:    mov r0, sp
94; CHECK-NEXT:    vmul.f32 s4, s0, s1
95; CHECK-NEXT:    vmul.f32 s4, s4, s2
96; CHECK-NEXT:    vmul.f32 s0, s4, s3
97; CHECK-NEXT:    vld1.64 {d2, d3}, [r0]
98; CHECK-NEXT:    add r0, sp, #16
99; CHECK-NEXT:    vmul.f32 s0, s0, s4
100; CHECK-NEXT:    vmul.f32 s0, s0, s5
101; CHECK-NEXT:    vmul.f32 s0, s0, s6
102; CHECK-NEXT:    vmul.f32 s0, s0, s7
103; CHECK-NEXT:    vld1.64 {d2, d3}, [r0]
104; CHECK-NEXT:    add r0, sp, #32
105; CHECK-NEXT:    vmul.f32 s0, s0, s4
106; CHECK-NEXT:    vmul.f32 s0, s0, s5
107; CHECK-NEXT:    vmul.f32 s0, s0, s6
108; CHECK-NEXT:    vmul.f32 s0, s0, s7
109; CHECK-NEXT:    vld1.64 {d2, d3}, [r0]
110; CHECK-NEXT:    vmul.f32 s0, s0, s4
111; CHECK-NEXT:    vmul.f32 s0, s0, s5
112; CHECK-NEXT:    vmul.f32 s0, s0, s6
113; CHECK-NEXT:    vmul.f32 s0, s0, s7
114; CHECK-NEXT:    vmov r0, s0
115; CHECK-NEXT:    mov pc, lr
116  %b = call float @llvm.vector.reduce.fmul.f32.v16f32(float 1.0, <16 x float> %a)
117  ret float %b
118}
119