1; RUN: llc -march=hexagon < %s | FileCheck %s 2; REQUIRES: asserts 3 4; Check that this doesn't crash. 5; CHECK: vand 6 7target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" 8target triple = "hexagon" 9 10%s.0 = type { [4 x <32 x i32>] } 11 12declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1>, <32 x i32>, <32 x i32>) #0 13declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32) #0 14declare <64 x i32> @llvm.hexagon.V6.vdealvdd.128B(<32 x i32>, <32 x i32>, i32) #0 15declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #0 16 17; Function Attrs: nounwind 18define void @f0() local_unnamed_addr #1 { 19b0: 20 %v0 = tail call <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32> undef, i32 16843009) 21 %v1 = getelementptr inbounds %s.0, %s.0* null, i32 0, i32 0, i32 3 22 br label %b1 23 24b1: ; preds = %b1, %b0 25 %v2 = phi i32 [ 0, %b0 ], [ %v11, %b1 ] 26 %v3 = and i32 %v2, 1 27 %v4 = icmp eq i32 %v3, 0 28 %v5 = select i1 %v4, <128 x i1> zeroinitializer, <128 x i1> %v0 29 %v6 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<128 x i1> %v5, <32 x i32> undef, <32 x i32> undef) 30 %v7 = tail call <64 x i32> @llvm.hexagon.V6.vdealvdd.128B(<32 x i32> undef, <32 x i32> %v6, i32 -32) 31 %v8 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v7) 32 %v9 = tail call <64 x i32> @llvm.hexagon.V6.vdealvdd.128B(<32 x i32> undef, <32 x i32> %v8, i32 -32) 33 %v10 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v9) 34 store <32 x i32> %v10, <32 x i32>* %v1, align 128 35 %v11 = add nuw nsw i32 %v2, 1 36 br label %b1 37} 38 39attributes #0 = { nounwind readnone } 40attributes #1 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvx,+hvx-length128b" } 41