1; RUN: llc -march=hexagon < %s | FileCheck %s 2 3target triple = "hexagon" 4 5; CHECK-LABEL: test1: 6; CHECK: r0 = ##1073741824 7define i32 @test1() #0 { 8entry: 9 %0 = tail call i32 @llvm.hexagon.S2.asr.i.r.rnd(i32 2147483647, i32 0) 10 ret i32 %0 11} 12 13; CHECK-LABEL: test2: 14; CHECK: r0 = ##1073741824 15define i32 @test2() #0 { 16entry: 17 %0 = tail call i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32 2147483647, i32 1) 18 ret i32 %0 19} 20 21; CHECK-LABEL: test3: 22; CHECK: r1:0 = combine(#0,#1) 23define i64 @test3() #0 { 24entry: 25 %0 = tail call i64 @llvm.hexagon.S4.extractp(i64 -1, i32 63, i32 63) 26 ret i64 %0 27} 28 29; CHECK-LABEL: test4: 30; CHECK: r0 = #1 31define i32 @test4() #0 { 32entry: 33 %0 = tail call i32 @llvm.hexagon.S4.extract(i32 -1, i32 31, i32 31) 34 ret i32 %0 35} 36 37; CHECK-LABEL: test5: 38; CHECK: r0 = ##-1073741569 39define i32 @test5() #0 { 40entry: 41 %0 = tail call i32 @llvm.hexagon.S4.subi.lsr.ri(i32 255, i32 -2147483648, i32 1) 42 ret i32 %0 43} 44 45declare i32 @llvm.hexagon.S2.asr.i.r.rnd(i32, i32) #0 46declare i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32, i32) #0 47declare i64 @llvm.hexagon.S4.extractp(i64, i32, i32) #0 48declare i32 @llvm.hexagon.S4.extract(i32, i32, i32) #0 49declare i32 @llvm.hexagon.S4.subi.lsr.ri(i32, i32, i32) #0 50 51attributes #0 = { nounwind readnone } 52 53