1; RUN: llc -march=hexagon < %s | FileCheck %s 2 3; Check that we generate zero-extends, instead of just shifting and oring 4; registers (which can contain sign-extended negative values). 5; CHECK: and(r{{[0-9]+}},#255) 6 7define i32 @fred(i8 %a0, i8 %a1, i8 %a2, i8 %a3) #0 { 8b4: 9 %v5 = insertelement <4 x i8> undef, i8 %a0, i32 0 10 %v6 = insertelement <4 x i8> %v5, i8 %a1, i32 1 11 %v7 = insertelement <4 x i8> %v6, i8 %a2, i32 2 12 %v8 = insertelement <4 x i8> %v7, i8 %a3, i32 3 13 %v9 = bitcast <4 x i8> %v8 to i32 14 ret i32 %v9 15} 16 17attributes #0 = { nounwind readnone } 18