1; RUN: llc -march=hexagon < %s 2; REQUIRES: asserts 3 4; The register coalescer created (via rematerialization) a definition of 5; a register (R0), which had "undef" flag set. This caused the def to be 6; ignored in the dependence graph, which then lead to an invalid instruction 7; move in the machine scheduler (and an assert). 8; The undef flags are already being cleared in the register cleanup, but 9; that happens after register allocation. The undef flags need to be cleared 10; earlier to avoid this issue. 11 12%0 = type <{ i8*, i8*, i16, i8, i8, i8 }> 13%1 = type { %2, %5, [3 x %3] } 14%2 = type { %3, %4, i16, i16 } 15%3 = type { i32, i32, i8, i8 } 16%4 = type { i32, i32, i32 } 17%5 = type { i8, i8, i8, i8, i32, i32, i16, i16, i32, i8, i8, i8, i32, i32, i16, i16, i32 } 18%6 = type { %7, i8, i16, i16, i8, i8, i8, i8, i8 } 19%7 = type { i32, i32, i16, i16, i16, i8 } 20 21@g0 = external constant %0, align 1 22 23; Function Attrs: nounwind readnone 24declare i32 @llvm.hexagon.M2.mpy.up(i32, i32) #1 25 26declare void @f0(%0*, i32, i32, i32, i32, i32) 27 28define void @f1(i8 zeroext %a0, %1* nocapture %a1, i8 zeroext %a2, i8 zeroext %a3) #0 { 29b0: 30 %v0 = getelementptr inbounds %1, %1* %a1, i32 0, i32 1, i32 9 31 %v1 = load i8, i8* %v0, align 1 32 %v2 = zext i8 %v1 to i32 33 %v3 = getelementptr inbounds %1, %1* %a1, i32 0, i32 2, i32 %v2 34 %v4 = tail call %6* @f2(i32 undef, i8 zeroext 0) 35 br i1 undef, label %b1, label %b5 36 37b1: ; preds = %b0 38 %v5 = tail call i32 @llvm.hexagon.M2.mpy.up(i32 undef, i32 undef) 39 %v6 = tail call i32 @llvm.hexagon.M2.mpy.up(i32 undef, i32 undef) 40 %v7 = zext i32 %v5 to i64 41 %v8 = zext i32 %v6 to i64 42 %v9 = add nuw nsw i64 %v8, %v7 43 %v10 = lshr i64 %v9, 5 44 %v11 = trunc i64 %v10 to i32 45 store i32 %v11, i32* undef, align 4 46 br i1 undef, label %b3, label %b2 47 48b2: ; preds = %b1 49 %v12 = getelementptr inbounds %3, %3* %v3, i32 0, i32 0 50 store i32 0, i32* %v12, align 4 51 tail call void @f0(%0* @g0, i32 undef, i32 0, i32 undef, i32 undef, i32 undef) 52 br label %b4 53 54b3: ; preds = %b1 55 br label %b4 56 57b4: ; preds = %b3, %b2 58 unreachable 59 60b5: ; preds = %b0 61 br i1 undef, label %b6, label %b7 62 63b6: ; preds = %b5 64 unreachable 65 66b7: ; preds = %b5 67 unreachable 68} 69 70declare %6* @f2(i32, i8 zeroext) 71 72attributes #0 = { nounwind "target-cpu"="hexagonv55" } 73attributes #1 = { nounwind readnone } 74