1; RUN: llc -march=hexagon < %s | FileCheck %s 2; Check that gp-relative instructions are being generated. 3 4; CHECK: r{{[0-9]+}} = memw(gp+#g0) 5; CHECK: r{{[0-9]+}} = memw(gp+#g1) 6; CHECK: if (p{{[0-3]}}) memw(##g2) = r{{[0-9]+}} 7 8@g0 = common global i32 0, align 4 9@g1 = common global i32 0, align 4 10@g2 = common global i32 0, align 4 11 12define i32 @f0(i32 %a0) #0 { 13b0: 14 %v0 = load i32, i32* @g0, align 4 15 %v1 = load i32, i32* @g1, align 4 16 %v2 = add nsw i32 %v1, %v0 17 %v3 = icmp eq i32 %v0, %v1 18 br i1 %v3, label %b2, label %b1 19 20b1: ; preds = %b0 21 %v4 = load i32, i32* @g2, align 4 22 br label %b3 23 24b2: ; preds = %b0 25 %v5 = add nsw i32 %v2, %v0 26 store i32 %v5, i32* @g2, align 4 27 br label %b3 28 29b3: ; preds = %b2, %b1 30 %v6 = phi i32 [ %v4, %b1 ], [ %v5, %b2 ] 31 %v7 = icmp eq i32 %v2, %v6 32 %v8 = select i1 %v7, i32 %v6, i32 %v1 33 ret i32 %v8 34} 35 36attributes #0 = { nounwind "target-cpu"="hexagonv5" } 37