1; RUN: llc -march=hexagon -mattr=+hvxv60,+hvx-length128b < %s | FileCheck %s 2 3; Test that we generate code for the vector byte enable store instrinsics. 4 5; CHECK-LABEL: f0: 6; CHECK: if (q{{[0-3]}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}} 7 8define void @f0(<32 x i32> %a0, i8* %a1, <32 x i32> %a2) local_unnamed_addr { 9b0: 10 %v0 = tail call <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32> %a0, i32 -1) 11 tail call void @llvm.hexagon.V6.vS32b.qpred.ai.128B(<128 x i1> %v0, i8* %a1, <32 x i32> %a2) 12 ret void 13} 14 15; Function Attrs: argmemonly nounwind 16declare void @llvm.hexagon.V6.vS32b.qpred.ai.128B(<128 x i1>, i8*, <32 x i32>) #0 17 18; CHECK-LABEL: f1: 19; CHECK: if (!q{{[0-3]}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}} 20 21define void @f1(<32 x i32> %a0, i8* %a1, <32 x i32> %a2) local_unnamed_addr { 22b0: 23 %v0 = tail call <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32> %a0, i32 -1) 24 tail call void @llvm.hexagon.V6.vS32b.nqpred.ai.128B(<128 x i1> %v0, i8* %a1, <32 x i32> %a2) 25 ret void 26} 27 28; Function Attrs: argmemonly nounwind 29declare void @llvm.hexagon.V6.vS32b.nqpred.ai.128B(<128 x i1>, i8*, <32 x i32>) #0 30 31; CHECK-LABEL: f2: 32; CHECK: if (q{{[0-3]}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}} 33 34define void @f2(<32 x i32> %a0, i8* %a1, <32 x i32> %a2) local_unnamed_addr { 35b0: 36 %v0 = tail call <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32> %a0, i32 -1) 37 tail call void @llvm.hexagon.V6.vS32b.nt.qpred.ai.128B(<128 x i1> %v0, i8* %a1, <32 x i32> %a2) 38 ret void 39} 40 41; Function Attrs: argmemonly nounwind 42declare void @llvm.hexagon.V6.vS32b.nt.qpred.ai.128B(<128 x i1>, i8*, <32 x i32>) #0 43 44; CHECK-LABEL: f3: 45; CHECK: if (!q{{[0-3]}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}} 46 47define void @f3(<32 x i32> %a0, i8* %a1, <32 x i32> %a2) local_unnamed_addr { 48b0: 49 %v0 = tail call <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32> %a0, i32 -1) 50 tail call void @llvm.hexagon.V6.vS32b.nt.nqpred.ai.128B(<128 x i1> %v0, i8* %a1, <32 x i32> %a2) 51 ret void 52} 53 54declare void @llvm.hexagon.V6.vS32b.nt.nqpred.ai.128B(<128 x i1>, i8*, <32 x i32>) #0 55declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32) #1 56 57attributes #0 = { argmemonly nounwind } 58attributes #1 = { nounwind readnone } 59