1; RUN: llc -march=hexagon < %s | FileCheck %s 2 3; Check that post-increment store instructions are being generated. 4; CHECK: memw(r{{[0-9]+}}++#4) = r{{[0-9]+}} 5 6define i32 @f0(i32* nocapture %a0, i16* nocapture %a1, i32 %a2) #0 { 7b0: 8 br label %b1 9 10b1: ; preds = %b1, %b0 11 %v0 = phi i32 [ %v10, %b1 ], [ 10, %b0 ] 12 %v1 = phi i32* [ %a0, %b0 ], [ %v8, %b1 ] 13 %v2 = phi i16* [ %a1, %b0 ], [ %v9, %b1 ] 14 %v3 = load i32, i32* %v1, align 4 15 %v4 = load i16, i16* %v2, align 2 16 %v5 = sext i16 %v4 to i32 17 %v6 = mul i32 %v3, 2 18 %v7 = add i32 %v6, %v5 19 store i32 %v7, i32* %v1, align 4 20 %v8 = getelementptr i32, i32* %v1, i32 1 21 %v9 = getelementptr i16, i16* %v2, i32 1 22 %v10 = add i32 %v0, -1 23 %v11 = icmp eq i32 %v10, 0 24 br i1 %v11, label %b2, label %b1 25 26b2: ; preds = %b1 27 ret i32 0 28} 29 30attributes #0 = { nounwind "target-cpu"="hexagonv5" } 31