1; Test fix for PR-13709. 2; RUN: llc -march=hexagon < %s | FileCheck %s 3; CHECK: f0 4; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32) 5; CHECK-NOT: lsr(r{{[0-9]+}}:{{[0-9]+}}, #32) 6 7; Convert the sequence 8; r17:16 = lsr(r11:10, #32) 9; .. = r16 10; into 11; r17:16 = lsr(r11:10, #32) 12; .. = r11 13; This makes the lsr instruction dead and it gets removed subsequently 14; by a dead code removal pass. 15 16 17%s.0 = type { i64 } 18%s.1 = type { i32 } 19 20define void @f0(%s.0* nocapture %a0, %s.1* nocapture %a1, %s.1* nocapture %a2, i8* nocapture %a3, i8* nocapture %a4) #0 { 21b0: 22 %v0 = getelementptr %s.0, %s.0* %a0, i32 1 23 %v1 = getelementptr %s.1, %s.1* %a2, i32 1 24 %v2 = getelementptr %s.1, %s.1* %a1, i32 1 25 %v3 = getelementptr i8, i8* %a4, i32 1 26 %v4 = getelementptr i8, i8* %a3, i32 1 27 br label %b1 28 29b1: ; preds = %b1, %b0 30 %v5 = phi i32 [ %v38, %b1 ], [ 2, %b0 ] 31 %v6 = phi i8* [ %v37, %b1 ], [ %v4, %b0 ] 32 %v7 = phi i8* [ %v36, %b1 ], [ %v3, %b0 ] 33 %v8 = phi %s.1* [ %v35, %b1 ], [ %v2, %b0 ] 34 %v9 = phi %s.1* [ %v34, %b1 ], [ %v1, %b0 ] 35 %v10 = phi %s.0* [ %v33, %b1 ], [ %v0, %b0 ] 36 %v11 = phi i8 [ undef, %b0 ], [ %v30, %b1 ] 37 %v12 = phi i8 [ undef, %b0 ], [ %v29, %b1 ] 38 %v13 = phi i64 [ undef, %b0 ], [ %v28, %b1 ] 39 %v14 = bitcast %s.1* %v8 to i32* 40 %v15 = bitcast %s.1* %v9 to i32* 41 %v16 = bitcast %s.0* %v10 to i64* 42 %v17 = tail call i64 @llvm.hexagon.A2.vsubhs(i64 0, i64 %v13) 43 %v18 = sext i8 %v12 to i32 44 %v19 = trunc i64 %v13 to i32 45 %v20 = trunc i64 %v17 to i32 46 %v21 = tail call i32 @llvm.hexagon.C2.mux(i32 %v18, i32 %v19, i32 %v20) 47 store i32 %v21, i32* %v14, align 4 48 %v22 = sext i8 %v11 to i32 49 %v23 = lshr i64 %v13, 32 50 %v24 = trunc i64 %v23 to i32 51 %v25 = lshr i64 %v17, 32 52 %v26 = trunc i64 %v25 to i32 53 %v27 = tail call i32 @llvm.hexagon.C2.mux(i32 %v22, i32 %v24, i32 %v26) 54 store i32 %v27, i32* %v15, align 4 55 %v28 = load i64, i64* %v16, align 8 56 %v29 = load i8, i8* %v6, align 1 57 %v30 = load i8, i8* %v7, align 1 58 %v31 = trunc i32 %v5 to i8 59 %v32 = icmp eq i8 %v31, 32 60 %v33 = getelementptr %s.0, %s.0* %v10, i32 1 61 %v34 = getelementptr %s.1, %s.1* %v9, i32 1 62 %v35 = getelementptr %s.1, %s.1* %v8, i32 1 63 %v36 = getelementptr i8, i8* %v7, i32 1 64 %v37 = getelementptr i8, i8* %v6, i32 1 65 %v38 = add i32 %v5, 1 66 br i1 %v32, label %b2, label %b1 67 68b2: ; preds = %b1 69 ret void 70} 71 72declare i64 @llvm.hexagon.A2.vsubhs(i64, i64) #1 73declare i32 @llvm.hexagon.C2.mux(i32, i32, i32) #1 74 75attributes #0 = { nounwind "target-cpu"="hexagonv5" } 76attributes #1 = { nounwind readnone "target-cpu"="hexagonv5" } 77