1; RUN: llc -march=hexagon -mv67t -debug-only=pipeliner < %s 2>&1 | FileCheck %s 2; REQUIRES: asserts 3 4; Test that the artificial dependencies have been created. 5 6; CHECK: Ord Latency=0 Artificial 7 8define void @bkfir(i32* nocapture readonly %in, i32* nocapture readonly %coefs, i32 %tap, i32 %length, i32* nocapture %out) local_unnamed_addr #0 { 9entry: 10 %0 = bitcast i32* %out to i64* 11 %cmp141 = icmp sgt i32 %length, 0 12 br i1 %cmp141, label %for.body.lr.ph, label %for.end52 13 14for.body.lr.ph: 15 %1 = bitcast i32* %coefs to i64* 16 %cmp8127 = icmp sgt i32 %tap, 0 17 br i1 %cmp8127, label %for.body.us.preheader, label %for.body.lr.ph.split 18 19for.body.us.preheader: 20 br label %for.body.us 21 22for.body.us: 23 %add.ptr.us.phi = phi i32* [ %add.ptr.us.inc, %for.cond7.for.end_crit_edge.us ], [ %in, %for.body.us.preheader ] 24 %i.0143.us = phi i32 [ %add51.us, %for.cond7.for.end_crit_edge.us ], [ 0, %for.body.us.preheader ] 25 %optr.0142.us = phi i64* [ %incdec.ptr49.us, %for.cond7.for.end_crit_edge.us ], [ %0, %for.body.us.preheader ] 26 %2 = bitcast i32* %add.ptr.us.phi to i64* 27 %incdec.ptr.us = getelementptr inbounds i32, i32* %add.ptr.us.phi, i32 2 28 %3 = bitcast i32* %incdec.ptr.us to i64* 29 %4 = load i64, i64* %2, align 8 30 %incdec.ptr1.us = getelementptr inbounds i32, i32* %add.ptr.us.phi, i32 4 31 %5 = bitcast i32* %incdec.ptr1.us to i64* 32 %6 = load i64, i64* %3, align 8 33 %_Q6V64_internal_union.sroa.0.0.extract.trunc.us = trunc i64 %6 to i32 34 %_Q6V64_internal_union2.sroa.3.0.extract.shift.us = lshr i64 %4, 32 35 %_Q6V64_internal_union2.sroa.3.0.extract.trunc.us = trunc i64 %_Q6V64_internal_union2.sroa.3.0.extract.shift.us to i32 36 %7 = tail call i64 @llvm.hexagon.A2.combinew(i32 %_Q6V64_internal_union.sroa.0.0.extract.trunc.us, i32 %_Q6V64_internal_union2.sroa.3.0.extract.trunc.us) 37 %add.ptr.us.inc = getelementptr i32, i32* %add.ptr.us.phi, i32 4 38 br label %for.body9.us 39 40for.body9.us: 41 %j.0137.us = phi i32 [ 0, %for.body.us ], [ %add.us, %for.body9.us ] 42 %x0x1.0136.us = phi i64 [ %4, %for.body.us ], [ %10, %for.body9.us ] 43 %x2x3.0135.us = phi i64 [ %6, %for.body.us ], [ %11, %for.body9.us ] 44 %x1x2.0134.us = phi i64 [ %7, %for.body.us ], [ %13, %for.body9.us ] 45 %iptrD.0133.us = phi i64* [ %5, %for.body.us ], [ %incdec.ptr13.us, %for.body9.us ] 46 %iptrC.0132.us = phi i64* [ %1, %for.body.us ], [ %incdec.ptr11.us, %for.body9.us ] 47 %sum0.0131.us = phi i64 [ 0, %for.body.us ], [ %18, %for.body9.us ] 48 %sum1.0130.us = phi i64 [ 0, %for.body.us ], [ %19, %for.body9.us ] 49 %sum2.0129.us = phi i64 [ 0, %for.body.us ], [ %20, %for.body9.us ] 50 %sum3.0128.us = phi i64 [ 0, %for.body.us ], [ %21, %for.body9.us ] 51 %incdec.ptr10.us = getelementptr inbounds i64, i64* %iptrC.0132.us, i32 1 52 %8 = load i64, i64* %iptrC.0132.us, align 8 53 %incdec.ptr11.us = getelementptr inbounds i64, i64* %iptrC.0132.us, i32 2 54 %9 = load i64, i64* %incdec.ptr10.us, align 8 55 %incdec.ptr12.us = getelementptr inbounds i64, i64* %iptrD.0133.us, i32 1 56 %10 = load i64, i64* %iptrD.0133.us, align 8 57 %incdec.ptr13.us = getelementptr inbounds i64, i64* %iptrD.0133.us, i32 2 58 %11 = load i64, i64* %incdec.ptr12.us, align 8 59 %_Q6V64_internal_union14.sroa.0.0.extract.trunc.us = trunc i64 %10 to i32 60 %_Q6V64_internal_union14.sroa.4.0.extract.shift.us = lshr i64 %10, 32 61 %_Q6V64_internal_union19.sroa.3.0.extract.shift.us = lshr i64 %x2x3.0135.us, 32 62 %_Q6V64_internal_union19.sroa.3.0.extract.trunc.us = trunc i64 %_Q6V64_internal_union19.sroa.3.0.extract.shift.us to i32 63 %12 = tail call i64 @llvm.hexagon.A2.combinew(i32 %_Q6V64_internal_union14.sroa.0.0.extract.trunc.us, i32 %_Q6V64_internal_union19.sroa.3.0.extract.trunc.us) 64 %_Q6V64_internal_union24.sroa.0.0.extract.trunc.us = trunc i64 %11 to i32 65 %_Q6V64_internal_union29.sroa.3.0.extract.trunc.us = trunc i64 %_Q6V64_internal_union14.sroa.4.0.extract.shift.us to i32 66 %13 = tail call i64 @llvm.hexagon.A2.combinew(i32 %_Q6V64_internal_union24.sroa.0.0.extract.trunc.us, i32 %_Q6V64_internal_union29.sroa.3.0.extract.trunc.us) 67 %14 = tail call i64 @llvm.hexagon.M7.dcmpyrwc.acc(i64 %sum0.0131.us, i64 %x0x1.0136.us, i64 %8) 68 %15 = tail call i64 @llvm.hexagon.M7.dcmpyrwc.acc(i64 %sum1.0130.us, i64 %x1x2.0134.us, i64 %8) 69 %16 = tail call i64 @llvm.hexagon.M7.dcmpyrwc.acc(i64 %sum2.0129.us, i64 %x2x3.0135.us, i64 %8) 70 %17 = tail call i64 @llvm.hexagon.M7.dcmpyrwc.acc(i64 %sum3.0128.us, i64 %12, i64 %8) 71 %18 = tail call i64 @llvm.hexagon.M7.dcmpyrwc.acc(i64 %14, i64 %x2x3.0135.us, i64 %9) 72 %19 = tail call i64 @llvm.hexagon.M7.dcmpyrwc.acc(i64 %15, i64 %12, i64 %9) 73 %20 = tail call i64 @llvm.hexagon.M7.dcmpyrwc.acc(i64 %16, i64 %10, i64 %9) 74 %21 = tail call i64 @llvm.hexagon.M7.dcmpyrwc.acc(i64 %17, i64 %13, i64 %9) 75 %add.us = add nuw nsw i32 %j.0137.us, 4 76 %cmp8.us = icmp slt i32 %add.us, %tap 77 br i1 %cmp8.us, label %for.body9.us, label %for.cond7.for.end_crit_edge.us 78 79for.cond7.for.end_crit_edge.us: 80 %22 = ashr i64 %18, 39 81 %23 = ashr i64 %19, 39 82 %24 = ashr i64 %20, 39 83 %25 = ashr i64 %21, 39 84 %26 = tail call i32 @llvm.hexagon.A2.sat(i64 %22) 85 %27 = tail call i32 @llvm.hexagon.A2.sat(i64 %23) 86 %28 = tail call i32 @llvm.hexagon.A2.sat(i64 %24) 87 %29 = tail call i32 @llvm.hexagon.A2.sat(i64 %25) 88 %_Q6V64_internal_union34.sroa.4.0.insert.ext.us = zext i32 %27 to i64 89 %_Q6V64_internal_union34.sroa.4.0.insert.shift.us = shl nuw i64 %_Q6V64_internal_union34.sroa.4.0.insert.ext.us, 32 90 %_Q6V64_internal_union34.sroa.0.0.insert.ext.us = zext i32 %26 to i64 91 %_Q6V64_internal_union34.sroa.0.0.insert.insert.us = or i64 %_Q6V64_internal_union34.sroa.4.0.insert.shift.us, %_Q6V64_internal_union34.sroa.0.0.insert.ext.us 92 %incdec.ptr41.us = getelementptr inbounds i64, i64* %optr.0142.us, i32 1 93 store i64 %_Q6V64_internal_union34.sroa.0.0.insert.insert.us, i64* %optr.0142.us, align 8 94 %_Q6V64_internal_union42.sroa.4.0.insert.ext.us = zext i32 %29 to i64 95 %_Q6V64_internal_union42.sroa.4.0.insert.shift.us = shl nuw i64 %_Q6V64_internal_union42.sroa.4.0.insert.ext.us, 32 96 %_Q6V64_internal_union42.sroa.0.0.insert.ext.us = zext i32 %28 to i64 97 %_Q6V64_internal_union42.sroa.0.0.insert.insert.us = or i64 %_Q6V64_internal_union42.sroa.4.0.insert.shift.us, %_Q6V64_internal_union42.sroa.0.0.insert.ext.us 98 %incdec.ptr49.us = getelementptr inbounds i64, i64* %optr.0142.us, i32 2 99 store i64 %_Q6V64_internal_union42.sroa.0.0.insert.insert.us, i64* %incdec.ptr41.us, align 8 100 %add51.us = add nuw nsw i32 %i.0143.us, 4 101 %cmp.us = icmp slt i32 %add51.us, %length 102 br i1 %cmp.us, label %for.body.us, label %for.end52 103 104for.body.lr.ph.split: 105 %30 = tail call i32 @llvm.hexagon.A2.sat(i64 0) 106 %_Q6V64_internal_union34.sroa.4.0.insert.ext = zext i32 %30 to i64 107 %_Q6V64_internal_union34.sroa.4.0.insert.shift = shl nuw i64 %_Q6V64_internal_union34.sroa.4.0.insert.ext, 32 108 %_Q6V64_internal_union34.sroa.0.0.insert.insert = or i64 %_Q6V64_internal_union34.sroa.4.0.insert.shift, %_Q6V64_internal_union34.sroa.4.0.insert.ext 109 br label %for.body 110 111for.body: 112 %i.0143 = phi i32 [ 0, %for.body.lr.ph.split ], [ %add51, %for.body ] 113 %optr.0142 = phi i64* [ %0, %for.body.lr.ph.split ], [ %incdec.ptr49, %for.body ] 114 %incdec.ptr41 = getelementptr inbounds i64, i64* %optr.0142, i32 1 115 store i64 %_Q6V64_internal_union34.sroa.0.0.insert.insert, i64* %optr.0142, align 8 116 %incdec.ptr49 = getelementptr inbounds i64, i64* %optr.0142, i32 2 117 store i64 %_Q6V64_internal_union34.sroa.0.0.insert.insert, i64* %incdec.ptr41, align 8 118 %add51 = add nuw nsw i32 %i.0143, 4 119 %cmp = icmp slt i32 %add51, %length 120 br i1 %cmp, label %for.body, label %for.end52 121 122for.end52: 123 ret void 124} 125 126declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1 127declare i64 @llvm.hexagon.M7.dcmpyrwc.acc(i64, i64, i64) #1 128declare i32 @llvm.hexagon.A2.sat(i64) #1 129 130attributes #0 = { nounwind "target-cpu"="hexagonv67t" "target-features"="+audio" } 131attributes #1 = { nounwind readnone } 132