1; RUN: llc -march=hexagon -O2 < %s | FileCheck %s 2; Looking for 3rd register field to be restricted to r0-r7. 3; v3:2=vdeal(v3,v2,r1) 4; CHECK: v{{[0-9]+}}:{{[0-9]+}} = vdeal(v{{[0-9]+}},v{{[0-9]+}},r{{[0-7]+}}) 5 6target triple = "hexagon" 7 8; Function Attrs: nounwind 9define void @f0(i16* %a0, i32 %a1, i8* %a2, i16* %a3) #0 { 10b0: 11 %v0 = alloca i16*, align 4 12 %v1 = alloca i32, align 4 13 %v2 = alloca i8*, align 4 14 %v3 = alloca i16*, align 4 15 %v4 = alloca i32, align 4 16 %v5 = alloca i32, align 4 17 %v6 = alloca i32, align 4 18 %v7 = alloca i32, align 4 19 %v8 = alloca i32, align 4 20 %v9 = alloca i16*, align 4 21 %v10 = alloca i16*, align 4 22 %v11 = alloca <16 x i32>, align 64 23 %v12 = alloca <16 x i32>, align 64 24 %v13 = alloca <32 x i32>, align 128 25 %v14 = alloca <16 x i32>, align 64 26 %v15 = alloca <16 x i32>, align 64 27 %v16 = alloca <32 x i32>, align 128 28 %v17 = alloca <16 x i32>, align 64 29 %v18 = alloca <16 x i32>, align 64 30 store i16* %a0, i16** %v0, align 4 31 store i32 %a1, i32* %v1, align 4 32 store i8* %a2, i8** %v2, align 4 33 store i16* %a3, i16** %v3, align 4 34 %v19 = load i8*, i8** %v2, align 4 35 %v20 = getelementptr inbounds i8, i8* %v19, i32 192 36 %v21 = bitcast i8* %v20 to <16 x i32>* 37 %v22 = load <16 x i32>, <16 x i32>* %v21, align 64 38 store <16 x i32> %v22, <16 x i32>* %v12, align 64 39 store i32 16843009, i32* %v4, align 4 40 %v23 = load i32, i32* %v4, align 4 41 %v24 = load i32, i32* %v4, align 4 42 %v25 = add nsw i32 %v23, %v24 43 store i32 %v25, i32* %v5, align 4 44 %v26 = load i32, i32* %v5, align 4 45 %v27 = load i32, i32* %v5, align 4 46 %v28 = add nsw i32 %v26, %v27 47 store i32 %v28, i32* %v6, align 4 48 %v29 = load i16*, i16** %v0, align 4 49 store i16* %v29, i16** %v9, align 4 50 %v30 = load i16*, i16** %v3, align 4 51 store i16* %v30, i16** %v10, align 4 52 store i32 0, i32* %v8, align 4 53 br label %b1 54 55b1: ; preds = %b3, %b0 56 %v31 = load i32, i32* %v8, align 4 57 %v32 = load i32, i32* %v1, align 4 58 %v33 = icmp slt i32 %v31, %v32 59 br i1 %v33, label %b2, label %b4 60 61b2: ; preds = %b1 62 %v34 = load <16 x i32>, <16 x i32>* %v11, align 64 63 %v35 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v34, i32 -1) 64 %v36 = load <16 x i32>, <16 x i32>* %v14, align 64 65 %v37 = load <16 x i32>, <16 x i32>* %v15, align 64 66 %v38 = call <32 x i32> @llvm.hexagon.V6.vswap(<64 x i1> %v35, <16 x i32> %v36, <16 x i32> %v37) 67 store <32 x i32> %v38, <32 x i32>* %v13, align 128 68 %v39 = load <32 x i32>, <32 x i32>* %v13, align 128 69 %v40 = call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v39) 70 store <16 x i32> %v40, <16 x i32>* %v14, align 64 71 %v41 = load <32 x i32>, <32 x i32>* %v13, align 128 72 %v42 = call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v41) 73 store <16 x i32> %v42, <16 x i32>* %v15, align 64 74 %v43 = load <16 x i32>, <16 x i32>* %v17, align 64 75 %v44 = load <16 x i32>, <16 x i32>* %v18, align 64 76 %v45 = load i32, i32* %v7, align 4 77 %v46 = call <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32> %v43, <16 x i32> %v44, i32 %v45) 78 store <32 x i32> %v46, <32 x i32>* %v16, align 128 79 br label %b3 80 81b3: ; preds = %b2 82 %v47 = load i32, i32* %v8, align 4 83 %v48 = add nsw i32 %v47, 1 84 store i32 %v48, i32* %v8, align 4 85 br label %b1 86 87b4: ; preds = %b1 88 ret void 89} 90 91; Function Attrs: nounwind readnone 92declare <32 x i32> @llvm.hexagon.V6.vswap(<64 x i1>, <16 x i32>, <16 x i32>) #1 93 94; Function Attrs: nounwind readnone 95declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 96 97; Function Attrs: nounwind readnone 98declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1 99 100; Function Attrs: nounwind readnone 101declare <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32>, <16 x i32>, i32) #1 102 103; Function Attrs: nounwind readnone 104declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1 105 106attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } 107attributes #1 = { nounwind readnone } 108